Why all VHDL codes (syntax) are not working in LabVIEW FPGA?

[MGR]

I am doing my research on motion control for three phase inducton motor.Where i am designing a DTC core( an algorithim implemented in VHDL / Xilinx software for motor control). The DTC core consists of seven different blocks and it is about 2500 lines VHDL code. i am try to implement this core in LabVIEW/ FPGA / CompactRIO hardware . I am using HDL interface node for each block.Finally each blocks are inter connected.

Problem faced during writing VHDL code in HDL interface node:

1. How to write GENERIC syntax e.g.  
   generic(N:integer:=8);
  since we can not entry any code in ENTITY.

2. If i am declaring a variable e.g.

    for i in N-1 downto 0 loop
     if (A(i) < B(i)) then
     LESSER <='1';GREATER<='0';EQUAL<='0';
     exit; ,

  FPGA Complier  is not understanding , What is N.
3. In HDL Interface node there is a option EXTRNAL FILE, What does it mean. Attaching external VHDL file or any other files.

4. Please try the following example using cRIO. This program is running sucessfully in Xilinx software but not in LabVIEW FPGA.

 ...........................................
VHDL Code for comparator circuit
------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity comparator is

generic(N:integer:=8);

  port(A,B:in std_logic_vector(N-1 downto 0);
      EQUAL,GREATER,LESSER:out std_logic);
end comparator;
architecture RTL1 of comparator is
begin
P1:process(A,B)
begin
for i in N-1 downto 0 loop
    if (A(i) < B(i)) then
    LESSER <='1';GREATER<='0';EQUAL<='0';
    exit;
  elsif (A(i)>B(i)) then
    GREATER <='1';LESSER <='0';EQUAL <='0';
    exit;
  elsif (A(i)=B(i))then
    EQUAL <='1';GREATER <='0';LESSER <='0';
    exit;
  end if;
end loop;
end process;
end RTL1;
--*************************

thank you

sahoo
sarat

[303032]

I am going through a similar issue. In my problem, its complaining that the constructs that I used are not understandable by the compiler. I wrote the codes in VHDL-2008.

So it seems that even after 10 years this problem is resolved.