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Want to use multiple FIFOs to speed up

Hello all,

I came across a problem when I changed my code on the FPGA. I am using PCIe-7851r card + Windows XP to control a device. There are 68 lines on the device that need to be controlled by digital pulses, 32 lines for Bus A, 32 lines for Bus B and 4 lines for Bus C. So previously I created a 32bit DMA FIFO with the length of 16,389. The commands are generated on the host PC and then transferred to the target. There are 3 groups of commands, respectively for Bus A (32 lines), B (32 lines) and C (4 lines). The 3 groups of data are interleaved into one big array, as demonstrated in many demos, and then indexed on the target. This works so far alright. The codes are in host.png and target.png.

But in this case the FPGA needs to run the loop 3 times to achieve the data for A, B and C. I tried to create more FIFOs to transfer the data. I.E., a U64 FIFO for A and B, and a U8 FIFO for C. The code is in target2.png. But I have no idea how to ensure them to run synchronously, and how I can send the data to the two FIFOs on the host PC.

 

So my questions are:

1. Shall I use two FIFOs if I want to speed up the digital output?

2. If the answer of 1 is yes, how can I synchronize the two FIFOs (both on host and target)?

3. Is there any other method I can use to speed up the data transferring and the digital output?

 

Thank you so much.

 

Regards,

Bo

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My blog Let's LabVIEW.
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Ok, I hope I understood everything you've written correctly. Here are my suggestions:

 

1. I don't think there is a problem with using two or to make it easier three FIFOs to transfer the data. The other way to speed up the output is by changing the loop timing but I guess, that is out of question.

2. If I'm not missing something here, you'll just have to take the two (or three FIFOs) and feed the respective array into each of those. There is no 100% secure way to ensure the data is sent at the same time on the host but you should be fine. You can check on the target by using "the timed out?" terminal. Put the FIFO nodes on the target in the same loop. Then each of those nodes will be executed once per iteration. If none of them times out you'll have an element for every line.

3. The speed of the output is only (almost) dependant on your loop timing (especially if you send rather large arrays into the FIFO so the bottleneck is not the host).

 

I hope this helps
Best

Bill

LabVIEW 2012 32 bit

I am not an expert!
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Hi Bill,

 

Thank you for your reply. That is really helpful. I will test the looping time first then (I should have done this at the first place:p). I may need to ask about how to optimize the code on the target later. But I will try it myself and see what I can get:) Cheers.

 

Regards,

Bo

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My blog Let's LabVIEW.
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