Using FIFOs or Saturation Arithmetics cause compilation error

[UlfN]

Hi!
I'm using cRIO-9002, cRIO-9102 and LV7.1 . Problem: When I'm using FIFOs or Saturation Arithmetics in FPGA-VI, the Xilinx-compilator generate an error. Why? Any suggestion. I've pasted two error messages from the compilation below. I've also added a saturation add-example that generates the error.

//Ulf

Using FIFO:
-------------------
Compiling vhdl file
C:/NIFPGA11/srvrTmp/LOCALH~1/TR78C1~1/rvi_fifo_write_325_29transducer_readaibuff

er_fpga.vhd in Library work.
ERROR:HDLParsers:163 -
C:/NIFPGA11/srvrTmp/LOCALH~1/TR78C1~1/rvi_fifo_write_325_29transducer_readaibuff

er_fpga.vhd Line 7. Unexpected symbol read: _.
ERROR:HDLParsers:163 -
C:/NIFPGA11/srvrTmp/LOCALH~1/TR78C1~1/rvi_fifo_write_325_29transducer_readaibuff

er_fpga.vhd Line 7. Unexpected symbol read: _.
ERROR:HDLParsers:164 -
C:/NIFPGA11/srvrTmp/LOCALH~1/TR78C1~1/rvi_fifo_write_325_29transducer_readaibuff

er_fpga.vhd Line 7. parse error, unexpected IDENTIFIER, expecting COMMA or COLON
-->
---------------------

Using Saturation Add:
---------------------
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity (Architecture ).
Set user-defined property "OPTIMIZE = off" for signal .
Entity analyzed. Unit generated.

Analyzing Entity (Architecture ).
ERROR:Xst:761 - C:/NIFPGA11/srvrTmp/LOCALH~1/ADD_31~1/rvi_add.vhd line 401: No default binding for component: . Ports do not match.
-->

Total memory usage is 49432 kilobytes


ERROR:Xflow - Program xst returned error code 6. Aborting flow execution...
-----------------------

[cfarmer]

Ulf,

Are you using a localized (non-english) version of LabVIEW?

Chris

[UlfN]

---

@cfarmer wrote:
Ulf,

Are you using a localized (non-english) version of LabVIEW?

Chris

---

Hi Chris!
No, I'm not using localized version of LabVIEW. The error is however found! For some reason, the compiler doesn't like that you change the VI-Server options in LabVIEW. "Exported VIs"-list have to be blank. The strange thing is that the compiler works fine, as long as there are no FIFOs or "Saturation"-VIs in the code.

//Ulf

ps. Have you noticed that "complex" data structures behaves strangley in the FPGA code? For instance, I had the "calibration"-cluster inside a cluster together with a boolean indicator(see below).



LSB Weight
Offset
<\Calibration>
CalibrationReady
<\Cluster>

It didn't work so good... It wasn't updated with the values. When I removed the "outer" cluster, everything works fine. Seems like LabVIEW-FPGA have some bugs...

ds.

[UlfN]

The data structure got messed up in the reply above. Sorry

{Cluster}
{Calibration}
LSBWeight
Offset
{\Calibration}
{\Cluster}

//Ulf

[UlfN]

---

@ulf N wrote:
The data structure got messed up in the reply above. Sorry

{Cluster}
{Calibration}
LSBWeight
Offset
{\Calibration}
{\Cluster}

//Ulf

---

... Too early in the morning, forgot the CalibrationReady-indicator.
{Cluster}
{Calibration}
LSBWeight
Offset
{\Calibration}
CalibrationReady
{\Cluster}