Timed Loops with External Clocks

[tsteel]

Hello All,

I was wondering if it is possible to create a single cycle timed loop which is clocked from an FPGA IO pin.  I am attempting to read high speed parallel data (10Mhz), perform a small amount of signal minimalisation and then transfer the result to a DMA FIFO for transfer to PC. The way that the parallel data is formatted is that there are 16 IO lines wired to the bus, and a 17th line for indicating a data ready status.  This is expected to come through at 10Mhz.  Can I use a timed loop from this 17th data line to ensure that my code runs at high speed?  For what its worth, I am using a PXI-7811 FPGA.

Thanks for your help,

Tristan

[Eli_S]

Hi,

What you are trying to do is use an external clock. Unfortunatelly you currently cannot use an external clock source in LabVIEW FPGA. I would recommend creating a derived clock that  matches the frequency of your external clock as closely as possible.

[tsteel]

Thanks for letting me know Eli, that saves a lot of confusion! 🙂

Is there any plans to implement this in future releases?

Cheers,
Tristan

[Eli_S]

Tirstan,

I am not sure whether or not there are plans to implement this on future releases 😞

[Rick_K]

Tirstan,

We are actively researching and working on this feature for a future release, so keep a look out for that. The type of application you described is exactly the type of problem we are looking to solve.

Thanks for your question

Rick Kuhlman | LabVIEW FPGA Product Manager | National Instruments | ni.com/fpga
Check out the new FPGA IPNet for browsing, downloading, and learning about LabVIEW FPGA IP Cores

[tsteel]

Thanks for the info, I look forward to the newer versions!

Cheers,
Tristan

[kevin.key]

Was this feature ever implemented?

[tannerite]

Hi Kevin,

This feature was implemented in our FlexRIO line of products. Most of the FlexRIO modules have external clock line inputs that can be exported to a Single-Cycle Timed Loop (SCTL). As for the R-Series and CompactRIO product lines, there is not a direct way to export a digital input line directly to an SCTL. You can either derive a new clock from the base clock of the FPGA or, if using a PXI system, export the 10 MHz backplane clock to an SCTL. 

One workaround that can be implemented is to have one SCTL reading a digital line, and another SCTL monitoring a local variable from the previous loop and checking for edges. I have attached a screenshot displaying a certain portion of code executing when the digital input has a rising edge (false to a true). This implementation will not have the accuracy of a directly exported clock; however, as long as you are using the default 40 MHz timebase for the timed loops reasonable frequency for the digital input, I don't believe you should miss any edges. 

Best,

[kevin.key]

What is the benefit of going through a local variable vs. just reading it in the same loop?

[tannerite]

Hi Kevin,

You can use one loop as well. If you are wanting to trigger multiple independent pieces of code, it could be useful to use a local variable to trigger other multiple parallel loops. I coded it this was for expandability; however, I think I overcomplicated things by adding two loops!

Best,

tannerite