Start up VI not recording/logging data until connected to PC

[HTaylor95]

Hi,

I have a RT VI running from a myRIO 1900, which is recording and saving values to a USB plugged into the device. When connect to a PC, and manually operating the Main VI on the myRIO, data is logged with no issues.

The problem arrises when setting the VI as the start up, in an attempt to make the myRIO record the data as a standalone. 'Data' is being logged to the USB, but these entries are all 0. 

Data from sensors is read via FPGA interface, but appears to stop when not being operated over LAN connection to the PC. My first thought is that there are dependencies that are missing that wont allow the myRIO to read data from the sensors, but I have not been successful in finding any missing. 

[ikaiser · Accepted solution]

Hey HTaylor,

Unfortunately many files are missing in the attached zip so I can only partially help. I noticed two things: The Open FPGA Reference VI configuration:

Not sure if it looks like this because the missing project and dependencies. Have you checked "Run the FPGA VI" on your end? Linking it to a Bitfile directly, and not the a VI.

Secondly, I noticed you are writing data from the FPGA to a Front Panel indicator and then reading if from there to lot it. As far as I know a Front Panel only exists on the PC(!) when the RT code is executed interactively from the PC - there is no Front Panel on the RT target. Please note that I am not sure about this as I did not work on myRIOs so far.

Try handing the data over from the deterministic loop to the logging one through a FIFO.

[HTaylor95]

Hi Ingo,

Thanks for helping me with this! 

Okay that makes sense, so it makes more sense for me to transfer the data from the myRIO to the RT via a FIFO and then from the RT to the PC over a different set of FIFOs? Or is it just the one set of FIFOs between the RT and PC? 

[ikaiser]

Sorry for the delayed answer.

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So it makes more sense for me to transfer the data from the myRIO to the RT via a FIFO and then from the RT to the PC over a different set of FIFOs? Or is it just the one set of FIFOs between the RT and PC? 

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The first version is the way I normally use. A DMA FIFO from FPGA to RT, then a Network Stream from RT to PC.

Generally it is possible to stream data from the FPGA directly to a PC, however that's a quite huge step (from deterministic FPGA with low memory to Ethernet/PC), therefore less common. Depending on your application maybe still a valid choice.

There is a page online explaining the main communication options between FPGA, RT, and PC (there called "HMI"). See chapter 4 / table 2 in: Understanding Communication Options Between the Windows HMI, RT Processor, and FPGA.