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Spikes in data when FIFO buffer is reduced

I am having an issue with having my RT host (cRIO9024) finishing its loop in time when I have any acceptable size of FIFO buffer (elements>50).  MyFPGA code is running at 50kHz.  Between 50-200 FIFO elements, data contains spikes which I believe is not being calculated in the FPGA.  Increasing the number of FIFO elements over 300 eliminates the spikes producing a clean signal, but my loop time grows to 3-4ms which I can't have.  Is my FPGA/HOST loop ratio too great to use FIFO? I have much more function to add to the RT Host in this 1kHz timed loop.  I'm trying to be as frugal with CPU load as I can and I'm already maxed out.

 

  

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Hi,

 

What version of LV are you using? I was unable to open your code with LV 2010. Could you please post some screenshots of your FIFO reads/writes from the FPGA and the host?

 

Allie

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Im using LAbview 2011 SP1.  I attached the host and fpga screenshots.

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Thanks for the screenshots! I'm upgrading my software now so I can look at your code more in depth.

 

Have you considered using polling methods for reading the FIFO instead of blocking? Not only does this reduce CPU usage, but hopefully will eliminate the FPGA FIFO time out problem.
https://decibel.ni.com/content/docs/DOC-15814

 

You could also try the method listed in this KB.
On each iteration of the loop, it checks to see how many elements are in the FIFO. If the FIFO is at the set size, it reads the data. If it isn't, it skips reading for that iteration until the FIFO is equal to or greater than the specified size. This should allow you to read 300 elements at once without increasing your loop rate to 3-4ms.

 

Let me know what you think! 

 

By the way, you can always call into support at 1-866-ASK-MYNI to speak directly to an engineer for a faster turnaround.

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OK.  I spent some time trying two of the five possible FIFO methods, 'Polling for Size' and IRQ.  I've eliminated the spikes with both of these methods, but still have a late finish problem along with an unstable data read issue based on the number of elements I use in the buffer. 

 

First Issue:  Late Finish

One thing I changed from the FIFO Methods example in the FPGA code was the IRQ trigger counts down from to 50 from 1000.  My logic reasoning is: if the FPGA is generating a data point every 20usec and I want data up at the RT host every 1000usec then I should interrupt at 50S/IRQ.  Is this correct?  If I use 1000S/IRQ then am I just updating the host every 20ms?  Well.  I see how I can reduce my CPU load from ~98 to 25% but my routine runs at no fast than 20ms.

 

Second Issue:  Unstable Data with smaller buffer

The unstable issue comes into play when I reduce the number of read elements below ~300 in an attempt to reduce RT host loop time.  Above 300, the data read is smooth (non-erratic), but my loop times are in the 3-4ms range.   If I need data every 1000 usec at the host from a FPGA routine running every 20usec, why wouldn't a element buffer size of 50 work?  50 produces very erratic data.  Moving it up to 100,150,200,250 still produces erratic data.  Is the 800MHz Power PC in this CPU too slow for this task?

 

 

I've uploaded some screen shots of the FIFO Test Method project running on my 9024/9116 system and some shots of the erratic and slow behavior using 1000S/IRQ interrupt along with the IRQ project.

 

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Colby,

 

I can continue working with you on the Service Request that we have. I can communicate quicker with you that way instead of on the forums.

 

Danny Funk

Applications Engineer

Danny Funk -- Senior Group Manager -- Software R&D -- NI
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Hi everyone,

 

Has this problem been solved? I am facing the same issue, except that changing the buffer size does not remove the spikes. I am using FlexRIO PXIe-7965R FPGA card and NI-5733 adapter module. I am under the impression this problem is not caused by the FIFO. Any input is greatly appreciated.

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In what clock domain is the AI node located on your FPGA VI? If the AI node isn't placed in the Sample Clock domain (or IOModClock if using an older version of the CLIP) then you will get glitches on your acquired data.

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double post

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David-A,

 

The 40 Mhz onboard clock is my sample clock. I am assuming you are suggesting that I place the AI node in the timed loop. This is what I have done, as you can see in the attached image. If that's not what you are implying, please explain your recommendation, as I am a beginner in FPGA programming. Thanks.

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