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Speed execution Loop in FPGA.

Dear All
How r u?
I hope every one is fine.
I'm using
NI-cRIO 9074
NI-9225 Module
I'm using the code in the attachment file to read from FPGA , the loop speed execution in this loop is 20micro second I need
to decrease execution to nanosecond.
Please send to me the solution of this issue.
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I am assuming the attached code is for the FPGA, and the host VI is reading from this VI? It may be helpful to see the host VI code in order to see if there is any way to speed up the execution of that, therefore speeding up the transfer of data. Simple steps you could possibly take would include closing any unnecessary applications which may be increasing CPU usage.
Pipelining would use the parallel processing nature of the FPGA to help the loop execute slightly faster, along with parallel loops and timed loops.
I believe the following link may be of some assistance to you also.
I hope this is of some assistance to you.

Message Edited by mickeyw on 08-04-2008 10:25 AM
Mike W
Applications Engineer
National Instruments UK&Ireland
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Hi Spring,
You are using a NI 9225 module, as such the fastest rate that it can read data is 50 kS/s which is 20 microseconds.
Your loop is going as fast as the module will allow, if you need something else to happen at a faster loop rate then you will need parallel loops.

The FPGA works on a 40 MHz clock, and the fastest rate is a single cycle loop.  A single tick takes 25 nanoseconds.
You can not use analogue modules inside a single cycle loop. This target only supports top-level FPGA clocks with the following frequencies (in Hz):
40MHz, 80MHz, 120MHz, 160MHz, 200MHz, so you could derive a 200 MHz clock that would give you a 5 nanosecond tick.

The FPGA produces truly parallel loops, but you are still restricted to  the clock speed for your fastest tick.

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