Hi Spring,
You are using a NI 9225 module, as such the fastest rate that it can read data is 50 kS/s which is 20 microseconds.
Your loop is going as fast as the module will allow, if you need
something else to happen at a faster loop rate then you will need
parallel loops.
The FPGA works on a 40 MHz clock, and the fastest rate is a single cycle loop. A single tick takes 25 nanoseconds.
You can not use analogue modules inside a single cycle loop. This target only supports top-level FPGA clocks with the following frequencies (in Hz):
40MHz, 80MHz, 120MHz, 160MHz, 200MHz, so you could derive a 200 MHz clock that would give you a 5 nanosecond tick.
The FPGA produces truly parallel loops, but you are still restricted to the clock speed for your fastest tick.
Cheers
Stephen