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Slow compilation using LV 8.6

Hi there,


When I try and compile my labview code it seems to be taking too long. I have left it for hours and still it has not completed. Last night I also left it compiling and it still had not done it after > 12 hours. Ive attached the code and also the compile server. The details of the  compile server do not change from what it reads in the screenshot. I am trying to perform across correlation and to view only a smallsample of points at a time in a graph.


If anyone could shed any light it would be much appreciated.   I am using LV 8.6 with a NI cRIO-9004 chassis with input card NI6215 and output card 9263.


Getting rather frustrating!! 


Thanks very much!

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Does this happen when you compile the LabVIEW FPGA Shipping Examples as well?  Have you ever been able to successfully compile?  Did it just start taking this long, or has it always been that way?  If you view your task manager to monitor the system resources being used, does LabVIEW or the Xilinx compiler take a large amount of CPU resources or change to 'Not Responding' when it is hanging at this point?  What OS are you running as well?


Sorry for the questions to start off with rather than answers, but I need a better idea of what type of issue this is.  It may come down to needing to repair/reinstall the FPGA module and compiler.


Jared Boothe
Staff Hardware Engineer
National Instruments
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Im using Windows XP. There wasn't a large amount of CPU used. I left it to compile over night and when I got back this morning I had an error message


*                       Advanced HDL Synthesis                          *

ERROR:Portability:3 - This Xilinx application has run out of memory or has encountered a memory conflict.  Current memory usage is 2090676 kb.  Memory problems may require a simple increase in available system memory, or possibly a fix to the software or a special workaround.  To troubleshoot or remedy the problem, first:  Try increasing your system's RAM.  Alternatively, you may try increasing your system's virtual memory or swap space.  If this does not fix the problem, please try the following:  Search the Answers Database at to locate information on this error message.  If neither of the above resources produces an available solution, please use Web Support to open a case with Xilinx Technical Support off of  As it is likely that this may be an unforeseen problem, please be prepared to submit relevant design files if necessary.
ERROR:Xflow - Program xst returned error code 19. Aborting flow execution... 




To be fair, this is pretty foreign to me. And what examples do you mean?

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The problem is due to the large array (1024 elements) that you build in the bottom loop. 1024 elements is not much for a processor, but is a lot of data to store on the FPGA at once. This is causing the FPGA compiler to compile and optimize for a long time and eventually the compiler runs out of memory on your development machine.


As a first test change the constant for the For loop to something small like 10 and then compile again.


In general you can not store large amounts of data at once in the diagram (wires) of a VI. Data can be stored inside of FIFOs or memory blocks without impacting the space required on the FPGA or creating long compile times. When processing or transfering data on or through the FPGA, handle only small amounts of data at a time. 

authored by
Christian L, CLA
Applications Engineering Senior Manager - Automotive and Transportation
NI - Austin, TX

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I removed the array but now It still wont compile. The error i get is "ERROR:Xflow - Program par returned error code 31. Aborting flow execution... "


By my reading this (i think) has something to do with the input pins of the fpga having different voltages.I don't know how to get around this. The code works fine on simulation mode but just won't compile! This is the compilation summary:




Status: Compilation failed.

Refer to the advanced tab for more information, or contact National Instruments technical support at

Compilation Summary

Logic Utilization:
  Number of Slice Flip Flops:       3,535 out of  28,672   12%
  Number of 4 input LUTs:           9,411 out of  28,672   32%

Device Utilization Summary:
   Number of BUFGMUXs                        2 out of 16     12%
      Number of LOCed BUFGMUXs               1 out of 2      50%
   Number of External IOBs                  76 out of 484    15%
      Number of LOCed IOBs                  76 out of 76    100%
   Number of MULT18X18s                     76 out of 96     79%
   Number of RAMB16s                        34 out of 96     35%
   Number of SLICEs                       6033 out of 14336  42%

Start Time: 11/12/2008 1:27:58 p.m.
End Time: 11/12/2008 1:47:20 p.m.



Any tips would be GREATLY appreciated....

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Message 5 of 6
Could you include your FPGA VI and project so that we can test it here and do more debugging. Based on the information so far it is very difficult to tell what may be going wrong.
authored by
Christian L, CLA
Applications Engineering Senior Manager - Automotive and Transportation
NI - Austin, TX

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