Single-Cycle Timed loop with ip hdl node

[CrazyEce91]

Hello,

   I have written vhdl code of a circuit that uses a clock, I have put the circuit in a SCTL and I want to operate with the clock frequency of the fpga( 40 MHz ) how can I achive this?

cheers

[cblanchard]

Hi CrazyEce91,

Have you seen this link?  It walks through the steps you can follow to configure the clock frequency of the FPGA.

Some other useful information about Single Cycle Timed loops can be found here. 

-cblanchard