Simple FPGA program execution time longer than I/O at requested low sample rate

[aetc]

Hardware:

1. 9025 RT controller
2. 9111 4-slot chassis
3. 3 installed C-series modules (1 x 9025 (32 channel voltage analog input, 2 x 9023 (8 channel current analog input)

FPGA:

I am currently using a total of 25 channels (9 of the voltage inputs and all 16 of the current inputs).

I currently have the sample rate set at 3600Hz which is at the very low end of the FPGA clock rate of 40MHz (=11,111 FPGA clock ticks). The sample count to read per loop iteration is 1571 and the DMA FIFO Buffer is set to the recommended 10 x  ChannelCount x SamplePerChannel.

Software summary:

I am doing simple waveform acquisition based on the LabVIEW project template for waveform acquisition (actually this has been simplified a simple array). The FPGA is currently set up to only do analog input via the 3 C-series modules before pipelining it and sending it to the RT controller via the DMA FIFO as recommended, i.e. no additional logic is done to the signal.

Question:

Initially the FPGA program would only compile if I had the Design Strategy changed from ‘Balanced’ to ‘Area’, otherwise I would get an error indicating that the estimated resources were not sufficient.

Once I got the FPGA program to compile OK, I found that the RT program would only run w/o an underflow error if I set the sample rate to the current setting of 3600Hz in which case everything was OK. Originally I was aiming for twice that rate, i.e. 7200Hz.

My question is as follows: Because the original sample rate of 7200Hz was already at the low end of what seemed available combined with the fact that I am not even using all of the available chassis slots or I/O channels, I am surprised that I am getting an underflow (i.e. the FPGA execution time is longer than the requested sample rate allows) error already with the 7200Hz sample rate. Do I need to change some basic configuration? or do I simply need to get a chassis with more resources?

[Joshua-B]

Hi aetc,

What is the specific error that you are encountering?  Do you have an error code and/or associated text?

[aetc]

Thanks for the reply -

The error came from the FPGA program when I set the sample rate to the 'high' value of 7.2 kHz (which is actually pretty slow considering the FPGA clock rate is 40MHz - the main point I as wondering about);

The error code, which was 5001, is a custom FPGA error code meaning an underflow error, i.e. where the actual FPGA loop rate ended up being larger than requested, i.e. because the I/O scan of the 25 channels could not be made quickly enough.

I've enclosed the project with the FPGA code. As mentioned this is a simplified version of the LabVIEW project template for waveform acquisition.

[Joshua-B]

Hi aetc,

I noticed that you have multiple I/O Nodes executing in series.  I would recommend combining these into a single node or at least executing them in parallel rather than in series.  I would expect that to speed up your loop execution rate.

[aetc]

Thanks for the heads-up, dumb of me not to see that (was not the intention) - a case of not seeing the forest for the trees. After I changed it to parallel acquisition, it did indeed go faster.

[Joshua-B]

You're very welcome!  I'm glad it's executing faster for you now.