I am completely new to cRIO and I am about to make a purchase but I cannot understand a how the sampling rate is defined for the different modules.
I understand that the sampling rate is generally defined as the total sampling rate of the module unless differently specified. Therefore my questions are
Thanks very much for your help (and for putting up with my ignorance)!
Solved! Go to Solution.
The sampling rate for different modules depends on whether you are using Scan Interface or FPGA mode for that module, the kind of module you are using, and how you read from it.
As for your question about whether the sample rate is partitioned between all channels or only the active channels, this depends on whether the module is multiplexed or not. The data sheet for the module should indicate if the specified maximum sampling rate is simultaneous (per channel) or scanned (divided between the channels being read).
Lastly, if your module is on-demand, you can read different channels at different rates by placing the reads in different loops, as long as you aren't trying to read faster than the specifications of your module. If your module has a set data rate, you can read your channels at the higher rate and then throw away samples on the slower channel to get down to the rate you want.
I'd also check this out:
thank you very much for your reply. From what I understand the multiplexer dictates the timing and how the signals are sampled partitioning the call to each channel with the same interval and sequentially for all of them no matter what. Therefore if I buy a
NI 9205 16 AI Differential/32 AI Single-Ended, ±200 mV to ±10 V, 16 Bit, 250 kS/s Aggregate
Conversion time (maximum sampling rate) CompactRIO & CompactDAQ chassis: 4.00 μs (250 kS/s)
I can acquire at most at 7.81 kHz since the sampling rate is not specified per channel, am I right?
Coincidentally, I happen to have a cRIO and 9205 sitting on my desk right now! So I ran a test where I read 1 channel in a loop and I was able to read at the max sampling rate (250 KS/s). Note that in order to achieve this sampling rate, I needed to change the Minimum Time Between Conversions property for the module in my LabVIEW project.
After that, I tried read 2 channels in a loop and achieved sample rates of about 125 kS/s (250/2). 3 channels gave me about 83.3 kS/s (250/3). So it looks like the sample rate gets divided down based on the number of channels that you are actively reading, now the total number of channels available on the module (16 or 32, depending on which input mode you are using).
In these tests, I was reading all the channels in the same IO Node. I'm not sure what the behavior would be if I read these modules in different loops.
To directly answer your question, no, with a cRIO you don't have to divide down evenly. For example you could sample
And repeat the above loop. If the "on demand" module could sample at 200kSamp/sec then you'd be sampling AI0 at ~100kSamp/sec, AI1,2 at ~50kSamp/sec
Thank you very much! Actually this solves my problems since I have 10 sensors and I need high frequency only for 2 of them
That is not possible. I get the following error message while trying to compile.
"An FPGA I/O Node has duplicate terminals. Delete the duplicate terminal from the I/O Node."
This is likely dependent on which specific module you are using. I can see how some of the higher speed modules might not allow it.
In your opinion with a Ni 9208 module (500S/s aggregated) can I achieve this results? Sampling channels at different frequency sample in two while loops in FPGA? Example 4 channel at maximum frequency and 12 at a low frequency.