I need help about the Read/Write Control of FPGA Interface. I would like to connect TCP Read data out (string) directly to Read FPGA VI but the input is a FXP.... How can I do this ?
You need to convert your read data. What is the format of the data coming through the TCP connection?
I don't want to convert the data, this is 'binary' Word data coming from TCP (not ASCII coded) and I would like to have it directly at the input of the Read FPGA VI....
Thanks a lot for your help
I don't want to convert the data, this is 'binary' Word data coming from TCP (not ASCII coded)
You need to be a lot more specific. Is the binary word the binary equivalent of the fixed point data?
I have ASTERIX messages coming from TCP server, it's just series of bytes that make up messages.
I want to take these flow of bytes from the TCP block to go to the FPGA Read with an input of 8 bits (1 Bytes) and atfer to the input of my VHDL file with an input: in std_logic_vector(7 downto 0) ....
The problem is in Labview the output of the TCP block is a string and the input of the FPGA Read is a FXP ( I don't know if I can change it) and I can't connect the two blocks...
I attach a file that will be easier to understand.
Thanks in advance for your answer
Then change your FPGA control to be a byte (U8). On your host side, use the String To Byte Array and then Index Array to get the specific byte you want to write to the FPGA.
Thank you for your help.
I have another question, how can I optimize the latency between the TCP output and the moment when the data arrive in the FPGA when I have a stream of data.
I made a test with an oscilloscope to calculate the latency between the valid of the Eth Phy and a trigger on a pin of the SBRio 9651 when there is a new incoming data in the FPGA part, it's approximately 200-300µSec.
But the latency between two different bytes incoming in the FPGA when I send a number of bytes is approximately 1ms....
I have attached a test pattern.
You could try reading more bytes at a time and use a couple of DMA FIFOs for sending the data back and forth between the RT and the FPGA. This would allow for more data to be processed at a time.
I tried your solution but the transfer latency between two bytes from the RT to the FPGA it's again more than 100µs. The problem may be between the TCP and the byte array conversion. What is your point of view about my design in the capture file ?
I have another question about the serial part, it could be better if the two processes (tcp & serial) were separated in two loop no? The serial could slow down the TCP ?
1) You are still just reading 1 byte from the TCP. You should read all of the data that is available.
2) The String To Byte Array and its opposite are actually noops, meaning they actually do nothing. So those are not slowing you down one tiny bit.
3) Yes, I would have the TCP read and the FIFO write in one loop and then the FIFO read and the serial write in another loop. Then you make sure you are reading all of the data available from the FIFO to write to the serial port.