RT and FPGA timing issue

[nimi003]

Hi,

I am currently using a CompactRIO with an FPGA (cRIO 9037) and a linear drive with EtherCAT communication.

The position of the linear drive etc. is captured in the RT VI and my other sensor data (collected with the cRIO Modules) is evaluated with the FPGA.

For the RT I use a timed loop synchronized to my Scan Engine which is running at 2 ms (or 2000 µs) and for the FPGA I use a simple wait for 2000 µs in a while loop. So both loops should be running and collecting data at a rate of 0.5 kHz or a cycle time of 2 ms.

In both cases I am logging the time in ms with the help of a µs-timer.

I have the following problem:
when performing experiments, the RT loop runs slightly faster than the FPGA loop causing to gain a cycle every 7-8 s. For long experiments this leads to a shift of several seconds, so that I cannot use the data properly.

The weird thing is: when I look into the time data, I find that the RT is much more inaccurate (+-10% cycle time between each cycle, should be normal) but when I calculate the mean value of the cycle times they are both (RT and FPGA) at 2.0000 ms, which indicates that both should be running at the same cycle time overall.

How can I synchronize both (RT and FPGA) loops?
Is there a setting in the project tree that might help to synchronize both loops/clocks?

Moreover the problem did not appear with my old cRIO (9074 I think) but with the new updated one without any VI changes I got the problem explained above...

Maybe somebody can help..

Nico