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R Series IO Module in Simulation
NickAlias
Member
10-25-2017 04:09 AM - edited 10-25-2017 04:10 AM
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Hello everybody,
I'm trying to simulate an FPGA VI that targets a PXIe-7975R board with an NI 6584 IO Module. Simulating the FPGA VI itself works okay, however I also want to inspect I/O together with simulated host data.
To accomplish this, I created a host VI with an FPGA Desktop Execution Node, selected my Top Level FPGA VI - but the IO Module Ports and Pins are not listed under "Available Resources". The IO Module status (IO Module Properties -> Status) rightfully says "RIO device not detected." as I run this simulation on a regular PC - but that should not affect Simulation of those I/Os, right? I *can* see Basic FPGA I/Os, if I add them via "FPGA Target -> New -> New FPGA I/O", which then appear in the Execution Node Configuration Dialog. However, I can not add IO Module I/Os there.
To provide a minimum working example, I'll be showing what works and what does not. You can find attached pictures of a simple project configuration, FPGA and Host VIs as well as the FPGA Execution Node Configuration Dialog (where I would be expecting the IO Module Pins as I see them in the Project Explorer).
I'm not sure what I am missing, so maybe somebody can tell me...
nturley
NI Employee (retired)
02-07-2018 01:08 PM
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BTW, This isn't R Series, it's FlexRIO
I believe CLIP IO isn't supported with Desktop Execution Node. It is supported with 3rd party Simulation however so that might be a better fit for you. There are a lot of simulation features so it's easy to get them confused. 3rd party simulation is popular with FlexRIO customers because it allows you to get cycle-accurate behavior of the CLIP.
http://zone.ni.com/reference/en-XX/help/371599K-01/lvfpgaconcepts/fpga_simulation_intro/
