I have elaborated the step by step execution of the project and the corresponding errors simultaneously. 1) Created a FPGA compact RIO LabVIEW project. 2) Detected a cRIO 9039, NI 9221 module under RT , NI 9401 module under FPGA. 3) Created a FPGA program (used NI 9401 pin for taking a pulse input). 4) Built a logic for Measuring the pulse width and processed the same input and generated RPM as a output. 5) Created user shared variables and attached it to output values, one of them is RPM. 6) Compiled it. there were no timing error while compilatuion. We were able to see the RPM in front panel by using external pulse input and then generated .lvbitx file for the same. 7) Used the same .lvbtx file in system definition file of VERISTAND 2015 sp1 project. 😎 Exact location of .lvbitx file is under user shared variables. It has been successfully accepted by veristand and we were able to see the corresponding attached user shared variables used in FPGA program as in different input & output sections under it. 9) Critical point to be noted here is that whenever I am providing the .lvbitx file, some slots under custom device>>scan engine & ethercat>>local chassis section get disabled and enabled accordingly when used in LabVIEW FPGA project. Like here the slot where I used the NI 9221 module under RT section only got enabled and the NI 9401 module which I used for the FPGA program got disabled. Then In enabled section I was able to add the RT section modules and can further use it for different purposes. 10) Then by making generalized settings of controller like IP address, OS, etc. and with current configuration I deployed the project and successfully got readings once, but then the requirement was there to make changes in FPGA program. Done with it. Again Compiled it. Used newly generated .lvbitx file and repeated the steps. Ran the VERISTAND project and then got the following error. LabVIEW: File not found. The file might have been moved or deleted, or the file path might be incorrectly formatted for the operating system. For example, use \ as path separators on Windows, : on Mac OS X, and / on Linux. Verify that the path is correct using the command prompt or file explorer. ========================= NI-488: Nonexistent GPIB interface.

Real-Time Measurement and Control

NI-488 Nonexistent GPIB interface error while deploying FPGA bit file under custom device>>scan engine & ethercat>> ser shared variable in VERISTAND'15 SP1

I have elaborated the step by step execution of the project and the corresponding errors simultaneously.

1) Created a FPGA compact RIO LabVIEW project.

2) Detected a cRIO 9039, NI 9221 module under RT , NI 9401 module under FPGA.

3) Created a FPGA program (used NI 9401 pin for taking a pulse input).

4) Built a logic for Measuring the pulse width and processed the same input and generated RPM as a output.

5) Created user shared variables and attached it to output values, one of them is RPM.

6) Compiled it. there were no timing error while compilatuion. We were able to see the RPM in front panel by using external pulse input and then generated .lvbitx file for the same.

7) Used the same .lvbtx file in system definition file of VERISTAND 2015 sp1 project.

😎 Exact location of .lvbitx file is under user shared variables. It has been successfully accepted by veristand and we were able to see the corresponding attached user shared variables used in FPGA program as in different input & output sections under it.

9) Critical point to be noted here is that whenever I am providing the .lvbitx file, some slots under custom device>>scan engine & ethercat>>local chassis section get disabled and enabled accordingly when used in LabVIEW FPGA project. Like here the slot where I used the NI 9221 module under RT section only got enabled and the NI 9401 module which I used for the FPGA program got
disabled. Then In enabled section I was able to add the RT section modules and can further use it for different purposes.

10) Then by making generalized settings of controller like IP address, OS, etc. and with current configuration I deployed the project and successfully got readings once, but then the requirement was there to make changes in FPGA program. Done with it. Again Compiled it. Used newly generated .lvbitx file and repeated the steps. Ran the VERISTAND project and then got the following error.

LabVIEW: File not found. The file might have been moved or deleted, or the file path might be incorrectly formatted for the operating system. For example, use \ as path separators on Windows, : on Mac OS X, and / on Linux. Verify that the path is correct using the command prompt or file explorer.

=========================

NI-488: Nonexistent GPIB interface.