Hi,
I am using NI 9146 FPGA and 4 modules (NI 9239 - 2, NI 9205, NI 9264). I have used 4 FIFOs(I64 data type) in four separate while loops in one FPGA vi. I am reading those FIFOs in RT Target vi. If I use dummy data in FPGA vi (not the data from modules) then I am able to read the FIFO without getting full. When I run my actual FPGA vi in which data from AI modules is taken and processed through PID and output on AO, then two of the FIFOs gets full alternately. I mean 2 FIFOs out of four never get full. But the other two gets full/empty alternately. If one is full, other is empty and next cycle other gets full and first empty.
All the four loops in FPGA vi are running at same rate 100us. If I send simple addition/subtraction data through same loops and FIFOs with the same rate, none of the FIFOs get full at any time.
What could be the problems? I have attached my FPGA vi here.
Please help
Rashmi
