Benchtop Measurement and Test
Distributed Measurement and Control
Systems Engineering Software
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Provides support for NI data acquisition and signal conditioning devices.
Provides support for Ethernet, GPIB, serial, USB, and other types of instruments.
Provides support for NI GPIB controllers and NI embedded controllers with GPIB ports.
I've got 2 VIs running in parallel.
One is updating values at specific indexes in an array.
The other one is reading the array to deal with the values (passed to the FPGA into a DMA).
In order to limit memory allocation, i've been using RT FIFOs working on an array of specifc size.
Both my writer and reader maintain context of the same size in shift registers. So every read/write is based on an array of the same size.
The data sharing is pretty fast and timeouts are both set to 0. R/W method is set to polling.
My reader process do not necessarily need the latest data written, but it should read real fast (even not up to date data).
What happen is that, when I write into the RT FIFO (Writer process), it seems that it blocks the Read RT FIFO primitive for a few hunderd of microseconds.
Is there a way to share data with the reader NOT being blocked because the writer updates the array (memory) ?
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