Hello, please share your thoughts on the current issue I'm about to describe, and the code will be available below. I'm currently working on using both SPI and FIFO to transfer, read and write data from host PC to FPGA and vice versa. After successfully tested the SPI and confirmed that it worked, I moved to FIFO, and my intention was to capture an array of 8 bytes of data. The communication between the host PC and target FPGA went fine. However, only the first element was read at the output. I was told to check the target FPGA, but I couldn't figure out the problem. Perhaps someone could take a look at my code and provide some directions on how to capture all 8 elements? Thank you in advance.
