LabVIEW FPGA CLIP Node Compile Error

[Idle]

Hello NI,

I'm working on an application for my Single-Board RIO (sbRIO-9601) and have been battling with a compilation error when I try to compile my FPGA personality through the CLIP Node.  I have two .vhd files that I declare in my .xml file, and everything to this point works great.  I add Component Level IP to my project and drag it to the VI I've created under my FPGA.

Within the FPGA personality, I basically add some constants on the CLIP inputs and indicators to my CLIP outputs and attempt to save/compile.  With this simple configuration, I run into a compile error (ERROR:MapLib:820 - LUT4 symbol .... see trim report for details on which signals were trimmed).  If I go back to my VI and remove the indicators on the output (making the output pin of the CLIP connected to nothing), everything compiles just fine.

I have included screenshots, VHDL and LV project files.  What would be causing an indicator on the output of my VI to force compilation errors?

Without anything attached to the CLIP output, a successful compile... 

After output indicator is included with CLIP, failed compilation...

 

NI sbRIO 9601
LabVIEW 8.6.0
LabVIEW FPGA
Windows XP  (32-bit, English)
No conflicting background processes (no Google desktop, etc.)

Message Edited by Idle on 01-28-2009 11:36 PM

[RyanB · Accepted solution]

Generally a 'trim' error suggests that there is some missing IP.  Often a CLIP source file is missing or the path specified in the XML is incorrect.

In your case I believe there is an error in the XML declaration:

<CLIPDeclaration Name="RandomNumberGenerator">
  <FormatVersion>1.0</FormatVersion>
  <HDLName>RandomNumberGenerator</HDLName>
  <ImplementationList>
    <Path>urng_n11213_w36dp_t4_p89.vhd</Path>
    <Path>fifo2.vhd</Path>
  </ImplementationList>

This tells LV FPGA to expect a top level entity named 'RandomNumberGenerator' defined in one of two VHDL files.  However, I did not see this entity in either of your two files.  If urng_n11213_w36dp_t4_p89 is the top level entity, change the XML to instead define the HDLName tag as follows:

   <HDLName>urng_n11213_w36dp_t4_p89</HDLName>

Also - in your XML you define the 'oBits' CLIP output as a U32, however the VHDL port is defined as an 89 bit vector:

oBits : out std_logic_vector(89-1 downto 0)

These definitions must match, and the maximum CLIP IO vector size is U32, therefore you will have to break up your oBits output into three U32 outputs.  I added the ports and changed your assignment logic as follows:

  oBits1(31 downto 0) <= srcs(31 downto 0);
  oBits2(31 downto 0) <= srcs(63 downto 32);
  oBits3(31 downto 0) <= "0000000" & srcs(88 downto 64);

These two changes resulted in a successful compile.

Note: The compiler only errors when you add the indicator because otherwise your CLIP code is optimized out of the design.  If IP is instantiated in a design, but nothing is connected to its outputs, does it consume any logic?  Most of the time the FPGA compiler is smart enough to take it out.

[Idle]

RyanB,

Thanks so much for the quick response.  You were right on with your solution!  I really appreciate you taking a look at this for me, I was really hitting a dead end.

I exactly made the changes you indicated and everything compiled as promised.  Hopefully I can pay back the favor to someone else on the forums soon!

Thanks again