I posted this to ni.com/powerdev Also posting here in hopes of more viewership.
we are working on a power converter controlled using the GPIC platform (sbRIO-9607 + NI 9683 mezzanine card). We are using the LVTTL DIO's as outputs for controlling the DC pre-charge circuit. I know -- should have used the DO or RLY DO pins instead -- this can still be done but will require interface board redesign, layout and fabrication which I am hoping to avoid.
We are finding that upon powering on these are initialized as either high output or high impedance state. We have tried 1k pull downs to no avail. This is causing the pre-charge relays to close without a close command. After the controller boots up and our application starts running, these DIO pins are initialized and the relays open. Behavior is fine here on out. So we are exposed for some 20 odd seconds.
Is there a way to initialize these pins so that the output is low upon power on and stays low till commanded otherwise? I think that if there were a way to pre-load the bitfile to the FPGA instead of loading when the RT application initializes, that may solve this issue but I have not been able to find how to do this.
Thank you for you reading and any help is appreciated.
Check the manual (link below) on page 40 you can see a specification for the value of the pull-down resistor about 50 Ω.
Also, you can have your FPGA VI running at boot. Check it here: