Is there a bug in FlexRIO DRAM IDL driver?

[jiangliang]

I already wired a U512x1 ref to the DRAM Process VI, but when I double click the Process.vi, I still can only open the DRAMx2 v1, not the niInstr Memory DRAM U512 v1 FPGA lvclass:Process.vi?

Thanks!

[carmen9]

May I know what version are you using?

It seems that there is no Process.vi for all the other DRAM

[David-A]

You can't open it because it doesn't exist. The Process.vi has two implementations, x1 (for a single bank of dram) and x2 (for two banks of dram). Both the x1 and x2 process.vi are implemented in a way that is invariant of the data path width. However there are statically dispatched vis inside of the process vi that will change depending on the data path width which is why we have a create resources.vi for each viable data path width.