I'm doing a POC with PXIe-7846(slot 2) and PXIe-7856(slot 3) in PXIe-1085 chassis to generate two digital waveform (<=1MHz square wave) which should be phase sync'ed through PXIe-Clk100 backplane clock. According to information in this page(http://zone.ni.com/reference/en-XX/help/371508U-01/target2devicehelp/pxie_784x_5x_base_clocks/), I should just use the 100 MHz Clock base clock generated from the FPGA target to compile my VI and will get expected behavior. However, on an Oscilloscope, I'm seeing that the two generated generated digital waveforms don't have fixed phase relationship, which means the two bit files are not running at a same clock base. Very likely, they are running at the 100MHz clock base on the board. To further verify my thought, I compile the same VIs with a 100MHz clock derived from PXI_Clk 10MHz base clock. This time, the phase relationship is fixed. Check out the MP4 files. User manual of PXIe-1085 claims that PXIe_Clk100 is fed to all peripheral slots. Any idea? Bug?
Whether anybody has done this and can shed a light on me.
Software Details: LabVIEW FPGA Module version 2016 NI Hardware: PXIe-8880, PXIe-1085, PXIe-7846, PXIe-7856