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How to output a TTL line cRIO-9054 PFI0

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Hi all,


We have a 9054 that we need a single TTL signal from to control a switch and I was planning to use the PFI0 line for it. However I can't find an example of how to set it up except as a digital input (here).


It suggests it is possible in the manual but I can't find the right combination of things to allow it in LV. It doesn't appear at the FPGA level or at the DAQ/Scan engine level.





Can anyone point me in the right direction?


Many thanks


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perhaps this KB makes things a little clearer:

Although have a look at this:

Section "Shared trigger bus"

And finally the block diagram of such a cRIO:

cRIO-9054 Block Diagram - CompactRIO Controller Manual - National Instruments (


You have to install DAQmx-support on your cRIO in order to access the PFI0. After that this line should be directly available from the RT-part.


If you need access to this PFI0 from the FPGA you have to set a route between the one of lines between the DAQmx ASIC and the FPGA (the cRIO_Trigx lines). That is done by DAQmx Connect ; you can now use these lines from the FPGA code to either set or read the PFI0.


Regards, Jens

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Accepted by topic author PWoodward

The bit I was missing was to use Trig0 and to reverse the source and destination on the signal routing.

Certified LabVIEW Architect
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