I have an NI 5782 adapter module fitted to an NI 7935R FlexRIO controller. I would like to lock the adapter's internal sample clock to an external 10MHz signal fed in through the CLK IN port as per pages 9 and 10 of the 5782 user manual.
I have not been able to find much documentation explaining how to do this. (Previous discussion on this topic I have been able to find on this forum focused on IoModSyncClock backplane method.) I am using LabView 2016 and running a multi-sample CLIP.
I have tried using the User Command register as per the NI 5782 Multi Sample CLIP help page, but it throws an error telling me this can only be done using the 40MHz onboard clock, whereas I need to use the IO Module\Data Clock in order for the AI and AO to work properly.
Instructions for how to lock to a 10MHz clock applied to CLK IN would be greatly appreciated.
To lock to a 10MHz clock through the CLK IN terminal, you have to make sure that the external reference clock meets the spec stated in the manual.
Regarding the CLK IN option, you will need to specifcy a different user data clock setting. The default is 0 and only works with a 1GHz Class Clock. Since you are using a 10MHz clock you will need to use a setting in the 250MHz Class. The user data clock settings can be found in the labview help.
Check below for a zipped project, although the project attached is designed for PXIe-795X and PXIe-796X but it should be working fine with PXIe-7935R too. Finally, you have to right click the I/O Module CLIP in the project and go to properties. Choose Details and make sure IOModSync is enabled and using DStarA. Note that once you change this you must recompile, even though LabVIEW will not warn you.
Thank you for your response.
Can you tell me what value I am supposed to enter in the User Data 1 field in order to lock to 10MHz? I don't fully understand the table, but it looks like the lowest it will let me lock to is one-quarter of 250MHz (so 62.5MHz). The signal generator I am using to provide clocking signals only goes up to 200MHz, so I have been trying to clock the 5782 off both 10MHz and 62.5MHz. I have tried both square wave and sinewave, and the signals have an amplitude of 2 Vpp, which should be sufficient according the manual specs.
So far I still haven't been able to get the 5782 locking to either of these external clocking frequencies.
I have attached images of the HOST and FPGA code I am using. I have tried the versions of the FPGA code given in both the Getting Started example and the Clock Select example without success. Can you provide any further clues or guidance?
Cheers - G