Real-Time Measurement and Control

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How to deal with "expected" timing errors compiling FPGA

I keep getting timing errors in "non-diagram" components for clock frequencies I don't use (eg 80 MHz, 320). I find it annoying but I know if I recompile enough they'll go away (this is the solution I got from NI tech support). Does anyone have any workflows or secret compile options to make these go away? I'm imagining some sort of "keep compiling until it works" script.😠

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