My goal is to run FPGA code using Single Cycle Timed Loop using 3MHz or less frequency. The problem I am facing now is cRIO-9039's FPGA Target appears not supporting deriving the clock to less than 5MHz (1/8 derive rate of 40MHz).
I use IP Integration Node that only supports running inside of Single Cycle Timed Loop so using while loop seems not an option (I tried.. then complained).
The compile result says Maximum possible rate is 3.3MHz. So I should be able to compile my code just fine if I use 5MHz or slower rate.
Thank you in advance
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The problem I am facing now is cRIO-9039's FPGA Target appears not supporting deriving the clock to less than 5MHz (1/8 derive rate of 40MHz).
Are you getting an error? Or is it just not letting you type in a value less than 5MHz?
It lets me type the frequency but the adjusted (closest to requested) frequency is much higher.
For example, if I type 3MHz, it's only possible to make 4.69MHz. If I type 10Hz, still 4.69MHz.
I tried it on my side and 4.69MHz seems to be the lower limit.
I know you mentioned that you were seeing 3.3MHz in the compile results. Could you post a screenshot of this?
This specification has to do with the VCO operating range of the Xilinx Kintex-7 7K325T FPGA in the 9039. The datasheet for Kintex-7 FPGAs is found here.