Hi all
I have a cRIO with the following modules: 9233, 9229 and 9203 and want to read them synchronously. I have read in the following threads that you have to take into consideration that the modules have different input delays.
http://digital.ni.com/public.nsf/allkb/CAE12AA9BCAA51A48625722C004866F8?OpenDocumenthttp://digital.ni.com/public.nsf/allkb/74EB238E1BCADD528625735300681A7D?OpenDocument
I want to compensate for this delay by removing X samples from the beginning of the arrays from the modules with delays and now want to calculate X.
From the datasheets I found following
9233:
Input delay 25kHz: 12.8/fs+3us
9229:
Input delay: 38,4/fs+2.6us
(I am sampling with 25kHz)
I thought that this would mean that I should remove 13 samples from the beginning of 9233 and 38 samples from the beginning of 9229. However, this does not seem to give a correct result. I connected the same signal to an input of 9233 and an input of 9229. I have attached three images. One without any compensation, one with the compensation calculated above and the last where an additional 3 samples (41) are removed from the 9229.
Why is the above calculation not correct?
