How is the NI-9505 'current sense' measured?

[EthanStern]

I have a cRIO 9505 module and a closed loop current control FPGA program that is roughly based on the NI help file: ...\examples\CompactRIO\Module Specific\NI 9505\Current Loop\Current Loop - NI 9505 (FPGA).vi. 

In both the example and in my program, the reported current (FPGA I/O node 'current sense') is an integral part of the control scheme but I don't know units or how the number is being measured.  (The documentation leaves a little to be desired)

The following comment from the 9505 FPGA example file has me confused:

"The Trig AI is used to trigger sampling of the current. Sampling occurs at
half the PWM duty cycle time (high time). It takes 9 clock cycles, in this example,
from the time a trigger is sent until the current is actually sampled. Therefore, a
trigger is sent 9 clock cycles before the desired sampling point."

From this comment, it seems like the current sense I/O node is returning the instantaneous current.  However, since the motor control signal is PWM, the current during the high time should always be the same.  A PWM signal is either on or off.  If I only trigger a read during the high time, my duty cycle should be irrelevant, right?  So then how would this control loop function?  Either the 'current sense' value is not instantaneous or I'm misunderstanding the purpose of the 'Trig AI' boolean.

Secondly, how is the number of clock cycles between the trigger and 'current sense' read known?  The comment says exactly 9 clock cycles.  I know that FPGA and RT are deterministic but how can a programmer know the trigger delay with that amount of accuracy?

Thank you,

Ethan

[Eric_R]

Hi Eathan

In the current loop example it should read the ticks in terms of on or off clock cycles. This is then translated to represent current value in amps. For more information regarding the 9505 see the user manual here on page 8. Please let me know if this helps.

Message Edited by Support on 06-09-2009 03:21 PM

[EthanStern]

Thanks for taking the time to reply but that doesn't really help.  I have already seen the functional block diagram with the box that says 'current sense' on page 8 of the user manual and that does not at all answer the question about how the 9505 is measuring current.

It can't possibly be measuring current by counting (voltage on) ticks either because the impedance of the device I'm driving, in this case a solenoid, is unknown.

Also, back to my original questions, why is the PWM loop triggering a current sense read at the precise midpoint of the PWM high time and how is it known that this trigger should occur exactly nine (40MHz) clock cycles before the desired sample time.

Thanks,

Ethan

[Eric_R]

Hi Eathen

Sorry that the documentation did not contain the information you were looking for. The current sense I/O will read the current at the instant it is called upon. In the case of this example we read nine ticks in advance since this is the approximate time it takes for the command to reach the I/O sense. By doing this we try to gather the data right on the falling edge of the PWM cycle. By doing this the system is in the middle of settling and thanks to the inductance from the system you have connected it should represent a very close average current.The actual programming for the clock cycles is controlled by the compact RIO FPGA.

[gigiozzi]

Quoting:

 - By doing this we try to gather the data right on the falling edge of the PWM cycle. -

Is this right? My understanding is that by synchronising acquisition with the middle of the PWM high time I should avoid both the rising and the falling edge. Am I missing something?

This 9505 module is a bit of a nightmare: our research team is trying to understand the reasons behind some erratic current measurement values.

We are using it to drive a simple DC motor and we see some inconsistent readings when driving the motor at different PWM values (100% duty cycle gives accurate current readings, whereas at around 50% duty we receive badly underesttimated readings - a trustworthy oscilloscope was placed in the circuit to check the actual current value and compare it with the cRIO output). We suspect that there is something wrong with the way current is read (we have three cRIO 9505 modules and they all display a similar behaviour, so it must be a matter of electronics design, not a fault in our system). One of our electronic engineers even suspects that at some point the system is losing a bit in the ADC conversion, however, he says he'd need to see the actual electric diagram of the module in order to back up that statement. 

Interesting thread. I hope someone who has come across similar problems with the 9505 or who knows in detail how the current sensing hardware works will join in and contribute further. 

Regards,

Nic

[IanC_]

Nic,

I think you're right about sampling the current in the middle of the PWM high time.

I'm not an expert on the 9505, but I've had problems with erratic current readings in the past and found it helpful to increase the inductance.  The 9505 is designed to work with a minimum inductance of 500 uH, and simple DC motors can be significantly lower than this.  It's worth checking the spec of your motors and possibly adding an external inductor in series.

Regards,

Ian

[gigiozzi]

Ian

The rating for our motors is between 0.5 and 0.9 mH, so that would seem to fit the range you indicated. Nonetheless, since we don't really know where to turn in relation to this current sensing problem, we will try and increase the impedance. I, as one of the software developers, suggested that we get rid of the synchronisation loop altogether ad create a new logic of our own for FPGA current sensing.

I hope some more people will contribute. I will keep posting if we find out anything new.

NI is very reluctant at granting us access to their electric diagrams, so quite some reverse engineering work is awaiting us.

Nic 

Message Edited by gigiozzi on 11-17-2008 08:42 AM

[EthanStern]

It's good to see that others have something to contribute to this thread.  I think most of us can agree that triggering in the middle of the PWM high time is done to avoid the rising and falling edges.  As for the inductance issue, that could be part of my problem.  I'm interested to see if there are any other answers out there.

Is sampling during the PWM high time standard practice in motor drive current sense circuits?  I have used several different PWM drives all of which have current sense outputs but, until now, I never really pondered how this value was being magically output from the black box.

[Eric_R]

Hi Ethan

A problem faced when reading current information is that the voltage is rapidly fluctuating like in a PWM for instance there will be no steady current present. I would recommend modeling the current mathematically and using a deterministic loop to read at the average point in the current. 

[gigiozzi]

Eric,

Do you mean that the synchronisation with the middle point of the PWM high time could be creating problems if the transient fluctuation caused by the rising edge has not settled by then?

If that were the case, we could be sampling a point that is always above or below average. Hence the erratic reading which appears to be PWM-dependent. 

If we are driving a DC motor, the RLC circuit characteristic is influenced by motor speed, I believe. This means that if the motor is driven at variable speed, the circuit characteristic changes for different PWM values; it is therefore hard to create an accurate mathematical model of the transient response.

I have this other idea, on which I would appreciate input from other forum contributors. If we were to synchronise acquisition with not just one, but a number of points during the PWM high time (say 25, 50 and 75%, for instance) and then use the average of the three reading as the "sensed current", would that help?

Cheers

Nic