Real-Time Measurement and Control

cancel
Showing results for 
Search instead for 
Did you mean: 

FlexRIO Tick Count Roll Over

When designing an FPGA The Tick Count number is constantly running, but to prevent a rollover event and causing a dropped ADC sample, How can I control the resetting of this Tick Counter so that it is not rolling over in the middle of a cycle?  In my Application I need to determine when an ADC Sample has finished and the next sample begins.  I am determining that any period of Low longer than 50ns > 100ns is a low between samples and the next Data Clock is the beginning of the next ADC Sample.  If I can't prevent the Tick Count roll over, is there a better way of doing this?Delay >50ns or 2 FPGA clocksDelay >50ns or 2 FPGA clocks

0 Kudos
Message 1 of 1
(118 Views)