FlexRIO 7976 - data loss in Host-Target communication

[riccolisi]

My code in FPGA have two SCTL.

The first SCTLis at 5 MHz and read eight I64 elements a time from eight different Host-to-Target FIFOs.

The second SCTL is a 180 MHz and write eight I16 elements a time to eight different Target-to-Host FIFOs

The throughput on the backplane bus should be 5 MHz x 8 channels x 8 bytes + 180 MHz x 8 channels x 2 bytes = 2880 MB/s

Why do I lose often data on the communication if 2.88 GB/s is less than the 3.2 GB/s of FlexRIO 7976?

Do I have to consider even controls on FPGA VI that are written from Host?

Why I have no error of data loss?

The PXI chassis is PXIe-1085 12 GB/s and the controller is a PXI 8880.

Could someone help me?

Thank you very much

[Terry_ALE]

Where is the data loss occurring?

Can you swap the analog/digital input for known data in such as counters to allow to better understand the conditions that cause the data loss?

[riccolisi]

I notice the loss of data on the Host (Windows). I expect an exact number of bytes from each FIFO Target-to-Host. I count them on the Host when I read them. The Host waits until all data from FPGA arrive.

The process is described better in this way: I have 8 different I64 array in the Host. For each array I use a different FIFOs Host-to-Target. Parallelizing code, I write for each FIFO a costant number of elements per time in a while loop (only if there are sufficient empty elements).For each I64 element FPGA read  from one of these FIFOs, FPGA makes some computation and it sends me N different I16 elements in Target to Host FIFOs. This operation is made for all 8 input FIFOs. In the host I read about 100 elements at a time (actually if the number of elements in the FIFO is greater than 100 I read all the data in that FIFO)

For example if the size of one of the initial array in the Host is 307,200 elements and N is 44, I will expect from FPGA 307,200 *44 = 13,516,800 elements.

At the moment I have always the same initial array for the 8 processes and N is fixed. What I read now from the eight FIFO Target-to-Host is the same for all the 8 processes.

If a run continuosly my host VI after some iteration that works correctly it happens that it go in a wait state as some elements (more than 10%) has not arrived from some FIFOs .In this situation I notice that the elements arrived from a FIFO are different from another FIFO as if the missed elements are not at the end but spread over the array. It seem that in nominal condition the throughtput between FPGA and Controller is bigger than the one allowed and so data are loss during communication.

Another important thing is that if I write 100 elements at a time from Host to Target the Host VI run for some minutes but at a certain point it will stop to receive data from FPGA. While if I write 1000 elements it can stop even immediately at the first iteration and sure after a few iterations.

How DMA engine works?

Sorry for the long description and thank you for your time