Feedback on Getting Started with CompactRIO - Logging Data to Disk

[Daniel-H]

hutl,

At first look, it appears you may be losing your handle to the FPGA.

Try putting a shift register on your while loop for the device reference.

Daniel

[hutl]

Daniel,

thank you for your help. But I am sorry, I am not sure if I should put a shift register to my "real time" while loop or the FPGA part with the "FIFO write" and what data I should connect with it.

[Dan_N]

Hi Hutl,

The shift register would go in your while loop in the Real-Time code, where the FPGA VI Reference In inputs are. However, I'm not sure if that's the source of your problem. If your FIFO is overflowing, it's likely because you're not reading from it quickly enough. I would try lowering the number of elements that you are reading to 2000, or doubling the size of your FIFO. Also, you have  a decimate 1D array wired to a build 1D array in your RT code, which you don't need. 

Best,

Dan N

Applications Engineer

National Instruments 

[zatx]

I'm very new to FPGA programming, and am having trouble with FIFO data logging.  I've followed the tutorial, and it seems to work pretty well, but I can't figure out how to control the rate at which the FPGA writes to the FIFO.  The loop timer in the Flat Sequence is set to 1000 uSec, so I would expect the FIFO to get a new value at 1 kHz.  If I sample a 1 Hz sine wave, I get about 1700 samples per cycle.  What is the cause of that?  Also, there appears to be a slight discontinuity in the data at the peaks and troughs.  I assume this has something to do with the 500 "Number of Elements" and Array size setting, because if I change these values to 1000 it only occurs at the peaks.  My goal is to acquire continuos data at about 1 kHz, which shouldn't be a challenge for my hardware (9076, 9263, 9205).  Also, the top loop in the FPGA VI is an AO loop that outputs a sine wave.  I don't think it should affect the lower loop, but I could be wrong.  Thanks for any help!

[zatx]

Okay, I figured out that a large part of my problem is that my function generator doesn't output a very good sine wave.  That answers the second part of my questions, i.e. regarding the "discontinuity".  That being said, there is still an issue with timing.  I've narrowed it down to the size of the array and the for loop in the FPGA VI.  If I get rid of the for loop and run a single AI channel, the timing works perfectly.  If I add three more channels, and put the for loop back in as indicated in the tutorial, I get 4 samples per channel per while loop iteration, e.g. data sampling at 4 kHz instead of the 1 kHz that I would assume when the loop timer is set to 1000 uSec.  Is this caused by the for loop?

[Dave-C]

Hi zatx,

The first thing that I would change regarding this would be to move your Loop Timer vi to the first panel of the sequence structure.  I think that may help to get this under control.  I'd also be interested in getting some more information regarding the FIFO size and type, but I would like to get that info in a new thread, since this one is getting long and drawn out.  Since this is a different issue, we should put it in a new thread, and we'll work from there.

Regards,

-Dave C

[DPcard]

Hi, I'm new to FPGA programming so I've tried to use this tutorial as a bit of a starting block, and have already hit a snag.

I'm hoping this is probably as small silly error as they often tend to be....I've tried following the tutorial exactly and got it working no problem, but then altered the channels to sample from two seperate input modules. The result I get is an unspecified invoke error on the read in (-50400) when trying to read data from my NI-9213 together with my 9205. I thought it may have been a data type error and tried to combat this by converting all data to the apt FXP as an input to the FIFO in the FPGA VI. This has not worked. In an effort to troubleshoot I have tried simply scanning from the 9213 alone with no success, so I'm assuming it has something to do with this input module. 

I'll upload my code with this message, and help from anyone more experienced would be very much appreciated. Thanks.

[Dave-C]

Hi DPcard,

I want to check on a few things initially.  Were things working with only the 9205 providing data and the 9213 not included in the program and does this configuration still work?  Also, have you tried using the 9213 in a different slot of the RIO?  This error number is typically associated with a loss of communication to the FPGA, so I want to check a few things to make sure that nothing is significantly broken.  To that end, does an example referencing the 9205 work?  Are you seeing any errors in compilation?

Aside from these questions, I'd recommend moving the Loop Counter to the first panel of a sequence structure in your FPGA VI.  That's where it's designed to go, and while it isn't causing this problem, it's a better practice.

Regards,

-Dave C

[DPcard]

Hi Dave,

I'm not seeing any errors in compilation, and data transfer from the 9205 did work. I've also tried shifting the modules into different slots with no sucess.

My best guess is that this is some kind of underflow error into the FIFO as I'm asking the 9213 to supply data faster than it can?

Thanks for the help so far,

Dan

[Dave-C]

Hi Dan,

In that case, how quickly are you trying to acquire data from the 9213?  I could see that being an issue.  Typically speaking the 9213 has two acquisition speeds, a "High-Speed" acquisition at approximately 75 Hz, or a "High-Resolution" rate of approximately 1 Hz.  More info on those is available in the module's manual.

Regards,

-Dave C