FPGA tristate timing problem

[Drew_Sutton]

Problem: Not able to get the tri-state to operate as needed. See "timing diagram.jpg", top signal is a 6MHz clock, second signal "CYCLE" is 167nS pulse at a 1MHz rate, 3rd and 4th NA, 5th signal (bottom) is a 15 bit address bus this is what I want to tri-state.

What I tried is to invert CYCLE and control the FPGA I/O Method Node 'ENABLE' for the address lines thinking the address will be tristated except when CYCLE is low as shown in the timing diagram, but it wont work it is always enabled.

The VI in the zip has address enable fixed as enabled, to see what I was trying modify as follows:

In TOP_FPGA.vi delete 'enable address' from the lower 24Mhz loop and connect local variable CYCLE to ADDR OUT 'enable' pin.

What can I do to make this operate as intended.

Thanks,

Drew Sutton

[Robbob]

Drew,

I didn't have too much time to look over your project, since it would take a while to understand everything going on, but I did notice that in  your ADDRESS_FPGA.vi, you set enable AND try to write at the same time, without any sort of dataflow.  I don't believe this should be happening in parallel, enable your outputs first and then try and write.

Did you try building this off of This KB? I would recommend taking a look at that to make sure you are attempting to do the tri-state correctly.

[Drew_Sutton]

Rob,

You hit the nail on the head, I am still trying to get the data flow concept  to sink in.

The link was helpful.

Thanks,

Drew