FPGA to Variant issue

[jer02342]

I inherited a very complex data system and have only been using labview for 3 months. The issue I am having is that I have a cRIO running off of a FPGA bitfile. I changed the FPGA to reflect new module sets which works, but when I go to run the acquisition code, I get an Error -63195, The handle for device communication is invalid or has been closed. Restart the application. The code requires the FPGA REFOUT to be converted to a variant to work in the code. For some reason the FPGA refout is being converted to an empty variant, so when I convert back, there is just an empty FPGA refout

[Terry_ALE]

It is unclear why this would be done.

I see no benefit in doing this.

[jer02342]

I don't know why this was done either. I just inherited this code from my predecessor and cannot contact them due to "issues" 

[AndyClegg]

If you are new to LV, then there are a few subtle things around FPGA that you may not immediately grasp:

1. The FPGA code is compiled to a bitfile, and that bitfile is either deployed by the RT application (i.e. as part of its startup) or the bitfile is deployed manually to the FPGA with its run at startup set. Just mentioning this in case it isn't clear exactly what bitfile is loaded and running.
2. Are you sure the FPGA code is running - and not just executing once for example - it can be difficult to diagnose so it can be helpful to but something visual on - like a counter that is reported back to the RT, or flash of the user LED.

Even if the code was supposed to have been working, could somebody leaving have corrupted it to leave the next person (you) with a difficult to trace problem.

However, it seems this error has arisen after you have added the new IO module - so probably the above are not the issue.
There are a few links with this error code and different problems - so worth scanning these:
https://knowledge.ni.com/KnowledgeArticleDetails?id=kA00Z0000019MITSA2&l=en-GB
https://www.chiefdelphi.com/t/error-63195-on-dio-and-analog-opens/142429

https://forums.ni.com/t5/LabVIEW/FPGA-error-63195/td-p/1014763

https://www.chiefdelphi.com/t/crio-watchdog-fpga-error-63195/126806/8

[jer02342 · Accepted solution]

It turned out my variant was not empty, the issue was turning the variant back into an FPGA reference. I was using an empty FPGA reference, to get the correct reference, the original FPGA refout must be copied as a constant and used