Hi Again. I'm confused about the prior statement "nothing upstream can run until [the FPGA IO Node] finishes executing". Does that mean the inputs to the FPGA IO Node can't occur unit the FPGA IO Node runs first? I must be thinking backwards about "upstream". I think of upstream things occurring earlier and downstream things occurring later. Like a river flowing from left to right, the flow comes from the left, upstream, and flows downstream, to the right. So, if data flow is from left to right, is it correct to say "nothing to the right of the FPGA IO Node can run until the FPGA IO Node finishes executing"? Thanks, sorry for the confusion.
