FPGA-RT data transfer

[Davidkor]

I am sending some data from the RT VI (host) to a FPGA  with a NI-cRIO 9035. I noticed there are some inconsistencies in the data transfer between the two VIs. I have attached a image of how the FPGA is wired.

I saw online that data transfer between RT and FPGA using cluster is not advisable, but the different types of data transfer approaches that I saw e.g handshake, FIFO etc mostly work with single data type. Using them on my application might not be feasible (my intuition). How do I go about sending data between the VIs.

Note: The RT VI also receives data from a TCP connection in a while loop, does some calculation before sending the resulting cluster to the FPGA. 

[crossrulz]

How often are you sending updates to the FPGA?  If not often (more than several ms per data point), then you are probably fine with the cluster update.  However, you seem to be mixing things together in the cluster that do not actually belong together.  Break out the gains and test type into their own clusters or separate controls.  You only write to those when you actually need to.

[Davidkor]

I updated the FPGA VI based on your recommendation. But the problem still persists. I have attached the FPGA VI. 

How can I synchronize the timing between the RT and the FPGA VI?

Should the timing for each iteration in the RT VI equals to the wait in the FPGA VI?