FPGA Compile Server Error

[czaum]

Hello!

I tried to compile a FPGA VI with LV8.5 and the compile server stopped with this error message:

Mapping design into LUTs...
ERROR:MapLib:661 - LUT2 symbol
   "mytop/n_3491/n_3486/n_3475/n_3467/HiCompare/BU2/U0/gen_structure_logic.gen_n
   onpipelined.a_lt_ge_gt_le_b.i_gen_carry_chain_comp/sel_0_mux00001" (output
   signal=mytop/n_3491/n_3486/n_3475/n_3467/HiCompare/BU2/U0/gen_structure_logic
   .gen_nonpipelined.a_lt_ge_gt_le_b.i_gen_carry_chain_comp/sel<0>) has input
   signal "mytop/n_3491/n_3486/n_3475/n_3467/HiCompare/b<15>" which will be
   trimmed. See the trim report for details about why the input signal will
   become undriven.

I developed the VI with LV8.2 and could compile it without any errors. The VI contains a DMA-FIFO and several analog IO operations.
Can anyone tell me which part of the VI may cause that error?

Kind regards,
Christopher Zaum

[Ken_Tobler]

Hello!

Do you have Windows german?

Ty to set the regional settings in english and compile again:
http://digital.ni.com/public.nsf/allkb/A45687D827A81D6E86257195007807B3?OpenDocument

You can also try mass compiling your project to 8.5

Best regards
Ken

[czaum]

Thank you for this hint! I use a german windows xp with sp2.
I will try to compile the VI again with English language settings.

Best regards
Christopher

[czaum]

I recompiled the VI with english regional settings (us + uk) and it aborted with the same error.
As mentioned in the link above, I also switched off all other programms running in the background.
But the error still remains.

Could the problem be solved when I use Vista instead of XP?

Best regards
Christopher