Does the LVFPGA reset input clear all internal memory states when it is asserted so that it is essentially like starting with a brand new FFT with the next valid input? The help file says that it "clears all internal states" but I am unsure if this depletes all internal FIFOs, registers, etc.
This only clears sets of data inputs that have yet to be processed. FIFO's and other functions on the FPGA are unaffected. You would use the reset when you want to restart the FFT - since the throughput is several clock cycles, if you stop and then restart the FFT, it will still retain those past data sets that you put in and perform an FFT on them, which is obviously not the behavior you want if you are doing an FFT on a new signal.