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DMA FIFO Spikes?

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DMA FIFO Spikes?



Let me describe the problem:

I have a FlexRIO (5751+7961) in a PXI system with a PXIe-8133 RT controller. (LabView 2011 SP1)

The 5751 writes every 100µs data in a DMA FIFO and the RT controller reads it every 100µs.

But after reading it in the RT controller several spikes occur as shown in the attached figure.

The FPGA is also attached.


I tried many things, I really think that the spikes come from the DMA FIFO.

Can somebody help me?


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Message 1 of 10

Re: DMA FIFO Spikes?

ADC_StartConv is a PXI Trigger line. Every 100µs it triggers the measurement

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Message 2 of 10

Re: DMA FIFO Spikes?


Could you please attach the Project as ZIP so i can check on both, the FPGA and the RT Host VIs where the Datalogging takes place.

One thing that hit my eye was that you have a For loop with 3 iterations, but standard tunnels for the data so only the last iterations values are written.


furthermore I was wondering why you write to the FIFO with 100µs and also read with 100µs because you usually would aquire at a high rate but only read bigge blocks at a lower rate.

In this case I would suspect a problem with Reading and writing into the buffer like this, Did you observe overflow and underflow statusbits?


Using DMA FIFO to Develop High-Speed Data Acquisition Applications for Reconfigurable I/O Devices

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Message 3 of 10

Re: DMA FIFO Spikes?

Hi Alex Pi,


thank you for the fast answer!

I could mail you the whole project in 2 days, when I am back in my office... But I have to say that it is a big project.


About the 3 iterations: This was only a try, it calculated the mean value. I deleted it.

And the 100µs: It is a research project and we are controlling a motor. The FlexRIO acquires data, does some signal preprocessing and sends it to the realtime controller. The control loop is in the realtime part, because we want to do many changes there.


Yes, I am observing the error cluster in the RT part. Underflow (error code: -50400) and I am always ckecking, that Elements Remaining = 0.


It looks like it could be an underflow. I observed also another thing: The spike occurs when the raw data (I32) passes through zero.(The posted picture is already offset corrected.) I tried to find a data conversion problem without success.




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Message 4 of 10

Re: DMA FIFO Spikes?

the raw data type is I16

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Message 5 of 10

Re: DMA FIFO Spikes?

If the project as a whole is too big, seeing the portion of the host VI where you read from the DMA FIFO would be helpful.


I would be very surprised if the DMA FIFO was contributing to the bad values as it simply copies whatever values you put in. You can try testing this with your current configuration by replacing the FPGA I/O node with a constant or other known value and write that to the DMA FIFO instead.  Do you have any other instrument that can read the signal you're reading into the FPGA?

Alex Person
NI-RIO Product Support Engineer
National Instruments
Message 6 of 10

Re: DMA FIFO Spikes?

yes, please upload the Host vi, the fpga vi and the project file so we can see the config settings, if the whole of the project is to large.

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Message 7 of 10

Re: DMA FIFO Spikes?


Thank you for your idea. I replaced one FPGA I/O with a constant and now I don't think anymore that it is the DMA FIFO.

But we have still the same problem. 

Is it possible that the I/O need an I/O device clock to work? Is it OK how i use it? (In the oscilloscope examples the I/O are always used in a timed clock...)


We are reading the signal also with a tektronix oscillope and we have also a box (NI SMB-2145) to connect the FPGA to an signal generator. We get the spikes also in this, so I definitely have a software problem.


I attached the project file, the FPGA program and the RT part. In the RT part I used a probe to check the execution of the case structures. Elements Remaining is only on the first iteration bigger than 0 and the other case structure is never executed.

I think that the spikes come from the FPGA I/O because in the FPGA program the indicator "Oulier FPGA" is counting the spikes.


Do you have an idea what i could try next?

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Message 8 of 10
Accepted by topic author hazardous
08-27-2015 04:09 PM

Re: DMA FIFO Spikes?



finally we found a solution!!

I don't know why, but the problem was the FPGA VI. We did it like it is done in the NI5751 oscilloscope example with a state machine.


Maybe the I/O need the IO Module Clock 0 to work.


Thank you anyway!!

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Message 9 of 10

Re: DMA FIFO Spikes?

hazardous a écrit :

Maybe the I/O need the IO Module Clock 0 to work.



It DOES! This Clock, provide by the module, ensure that when calll the IO Node, there is a new value convert and available after the ADC.

Without this clock the IO node is call asynchronously at the top level clock.

Message 10 of 10