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I've started to develop RT code for cRIO application with DMA FIFO feature. Some very fundemental questions have
been hovering around in my mind. The DMA FIFO is supposed to be composed of two components (FPGA
side & RT side).
1. Is the total FIFO composed of FPGA side FIFO + RT Side FIFO?
2. The DMA FIFO size that I set inside the FPGA Target in project explorer refers to what(just FPGA
side FIFO or Total size)? If it is just FPGA side FIFO, how is the size of RT side FIFO set (is
it automatically assigned by RTOS depending on free memory)?
3. Also, the size set programatically using DMA-Configure is equivalent of setting the size
in project explorer?
4. Finally, How can I estimate the maximum size of FIFO that I'm allowed to use?
Thanx in advance for any replies.
Go to Solution.
1. Yes, atleast a DMA FIFO has these two sides
2. I just read in another reply that the size that you set for the FIFO in the project explorer is the size of the FIFO on the FPGA side. The size of the FPGA on the RT side is much larger (default being 10000 elements).
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