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Copiling Error with cRIO / 9211

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I'm getting the following error-message then I compile my VI:
 
ERROR:HDLParsers:3312 - "C:/NIFPGA82/srvrTmp/LOCALH~1/TEST_9~1/toplevel_gen.vhd" Line 1281. Undefined symbol 'GSR'.
ERROR:HDLParsers:1209 - "C:/NIFPGA82/srvrTmp/LOCALH~1/TEST_9~1/toplevel_gen.vhd" Line 1281. GSR: Undefined symbol (last report in this block)
ERROR:HDLParsers:850 - "C:/NIFPGA82/srvrTmp/LOCALH~1/TEST_9~1/toplevel_gen.vhd" Line 1436. Formal port mRegisterAccess does not exist in Component 'rvi_test_9211_FPGA'.
-->
Total memory usage is 107968 kilobytes
Number of errors   :    3 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)
ERROR:Xflow - Program xst returned error code 6. Aborting flow execution...
 
 
I have attached a picture with the VI I'm using (it's one of LabViews example VIs). I'm using LabView 8.2.1 and a cRIO-9004 with a 9211 Module.
 
 
Can anyone tell me what I'm doing wrong? Any help would be very appreciated.
 
cheers
miko
 
 
 


Message Edited by kein on 08-08-2008 07:09 AM
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Hi!

Which version of NI-RIO are you using?
There was an problem with the NI-RIO 2.1 Version which generate such problems.

Try installing NI-RIO 2.1.3 or later and it should resolve the problem.

Best regards
Ken
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Hello Ken,

 

thank you for your help. I installed NI-RIO 2.1.3, but I'm getting the same error as before:

 

ERROR:HDLParsers:3312 - "C:/NIFPGA82/srvrTmp/LOCALH~1/TEST_9~1/toplevel_gen.vhd" Line 1281. Undefined symbol 'GSR'.
ERROR:HDLParsers:1209 - "C:/NIFPGA82/srvrTmp/LOCALH~1/TEST_9~1/toplevel_gen.vhd" Line 1281. GSR: Undefined symbol (last report in this block)
ERROR:HDLParsers:850 - "C:/NIFPGA82/srvrTmp/LOCALH~1/TEST_9~1/toplevel_gen.vhd" Line 1436. Formal port mRegisterAccess does not exist in Component 'rvi_test_9211_FPGA'.
-->

Total memory usage is 107968 kilobytes

Number of errors   :    3 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR:Xflow - Program xst returned error code 6. Aborting flow execution...

 

What else can I try?

 

Best regards

miko

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Hi!

 

Does the compiler gives an error when you try to compile only a very simple program with only the while loop and one input of the modul (without Interrupt, without CJC, mutliple TCs and without the cluster)?

Does the compiler can compile a FPGA Program with only a while loop (without accessing the 9211)?

 

Regards
Ken

 

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Hello!

 

Thank you for your last suggestion. It didn't compile a simple while loop, but with the help of the errormessage I was able to fix the problem.

 

The problem was that somehow the LabView RT Version on the host and the remote system were different.

When I save the vi for the right version everything works fine.

 

With kind regards

 miko

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Miko,

 

Can you elaborate on how you fixed this issue?  I don't think the compile failure you saw would be root caused to the remote machine having a different version of LV.  I'd like to find out if there is a bug R&D can take action on.

 

Thanks,

 

Basset Hound

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Hi!

 

First I have to say that I'm just working a couple of days with cRIO, so I don't have too much experience with it and the whole configuration was done by my predecessor (not by me) which unfortuneatly I never met

 

In the picture you can see that the Labview Real Time versions are different (8.5 vs. 8.2) on my computer and the cRIO module.

 

So when I saved my vi I saved it for a previous Version (see picture).

 

Since then, I don't receive any compiling errors anymore.

 

with kind regards

miko

 

 

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