I attached images here to show my problem. There is an image showing all the software, hopefully proving I have all the correct drivers installed, and one showing the cRIO being "disconnected". I followed the steps of the support page about setting up a cRIO and the IP address for the device is also able to be pinged. I however do not know why it will not fully connect to the computer. Any help you could give would be greatly appreciated. Thanks!
I was able to get it to connect in NI Max. Now when I try to compile the code I receive this:
Target: FPGA Target (RIO0, cRIO-9073)
Build Specification: 9073 FPGA2
Top level VI: 9073 FPGA2.vi
Compiling on local compile server
Compilation Tool: Xilinx 12.4
Start Time: 2/24/2021 9:25:09 AM
Run when loaded to Fpga: FALSE
Design Strategy: Balanced
Synthesis Optimization Goal: Speed
Synthesis Optimization Effort: Normal
Map Overall Effort Level: High
Place and Route Overall Effort Level: Standard
Working Directory: C:\NIFPGA\compilation\AOWGFIFO2CJ_FPGATarget_9073FPGA2_7D678030
It says there is a communication error between the device and the compiler. Any ideas on what this could be?
This is the summary of the compiler:
LabVIEW FPGA: The compile worker cannot perform the compilation. The compile worker may be configured incorrectly for this compilation or it may be in an error state.
LabVIEW FPGA: The compilation cannot be performed by the compile worker. The compile worker may be configured incorrectly for this compilation, or it may be in an error state.
Click the 'Details' button for additional information.
Start Time: 9:25:09 AM
Total Time: 00:03:53