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Compile Worker 2018 and cRIO-9022 + Chassis cRIO-9118 FPGA build fails

Hello,

 

I have this issue with CRIO-9118 using the FPGA Compile worker 2018.

My LV is 18.0.1f4 (32-bit)

According to: http://www.ni.com/product-documentation/53056/en/

It (9022+9118) should be supported.

 

I can build for other newer FPGA targets fine, but the CRIO-9118 model fails.

 

Any inputs why this is?

Anyone using Linux Compile Server for 2018 who can try project?

 

*** compile worker ***

2019-09-30 11:16:17Z|INFO|SessionId=zglGY13|WorkerId=|JobId=|Setting info that should end up in the UI: Started work on job for capability:  'Xilinx 14.7'
2019-09-30 11:16:17Z|INFO|SessionId=zglGY13|WorkerId=|JobId=|UI info changed: Started work on job for capability:  'Xilinx 14.7'
2019-09-30 11:16:21Z|INFO|SessionId=zglGY13|WorkerId=|JobId=|UI info changed: Working on: Test_crio_9022/FPGA Target/FPGA_Main
2019-09-30 11:16:21Z|INFO|SessionId=zglGY13|WorkerId=sMw82a8|JobId=CAl43E9|Working on: Test_crio_9022/FPGA Target/FPGA_Main
2019-09-30 11:16:21Z|INFO|SessionId=zglGY13|WorkerId=sMw82a8|JobId=CAl43E9|starting step 1 (CoreGenerator)
2019-09-30 11:16:21Z|INFO|SessionId=zglGY13|WorkerId=sMw82a8|JobId=CAl43E9|starting step 2 (PlanAhead)
2019-09-30 11:16:21Z|INFO|SessionId=zglGY13|WorkerId=sMw82a8|JobId=CAl43E9|Running process: /usr/local/natinst/NIFPGA/programs/xilinx14_7/PlanAhead/bin/planAhead -mode batch -source "/usr/local/natinst/NIFPGA/jobs/CAl43E9_sMw82a8/planAheadScript.tcl"
2019-09-30 11:16:39Z|INFO|SessionId=zglGY13|WorkerId=sMw82a8|JobId=CAl43E9|starting step 3 (Synthesize - XST)
2019-09-30 11:16:40Z|INFO|SessionId=zglGY13|WorkerId=sMw82a8|JobId=CAl43E9|Running process: /usr/local/natinst/NIFPGA/programs/xilinx14_7/ISE/bin/lin/xtclsh /usr/local/natinst/NIFPGA/jobs/CAl43E9_sMw82a8/synthesize.tcl
2019-09-30 11:16:40Z|INFO|SessionId=zglGY13|WorkerId=sMw82a8|JobId=CAl43E9||3|Synthesize - XST|DbgStdErr|Synthesis process returned error code: 255
2019-09-30 11:16:40Z|ERROR|SessionId=zglGY13|WorkerId=sMw82a8|JobId=CAl43E9|The Unit Of Work (path: /usr/local/natinst/NIFPGA/jobs/CAl43E9_sMw82a8) did not finish properly because of an exception: The step 'Synthesize - XST' errored and we were asked to quit on error.
2019-09-30 11:16:40Z|ERROR|SessionId=zglGY13|WorkerId=sMw82a8|JobId=CAl43E9|NI.LV.FPGA.CompileWorkerUI.UowQuitException: The step 'Synthesize - XST' errored and we were asked to quit on error. ---> NI.LV.FPGA.CompileWorkerUI.UowQuitException: Synthesis process returned error code: 255    at NI.LV.FPGA.CompileWorkerUI.IseStepExecutor.ThrowIfError (NI.LV.FPGA.CompileWorkerUI.UowState uowState, System.String processName, Int32 result) [0x00000] in <filename unknown>:0     at NI.LV.FPGA.CompileWorkerUI.IseStepExecutor.TclSynthesize (NI.LV.FPGA.CompileWorkerUI.UowState uowState, IDictionary`2 globalArguments, IDictionary`2 arguments) [0x00000] in <filename unknown>:0     at NI.LV.FPGA.CompileWorkerUI.IseStepExecutor.ExecuteCapabilityStep (NI.LV.FPGA.CompileWorkerUI.UowState uowState, IDictionary`2 globalArguments, NI.LV.FPGA.CompileWorkerUI.SimpleUowStep step) [0x00000] in <filename unknown>:0     at NI.LV.FPGA.CompileWorkerUI.SimpleUowStep.Run (NI.LV.FPGA.CompileWorkerUI.UowState uowState, IDictionary`2 globalParameterList, IUowStepExecutor executor) [0x00000] in <filename unknown>:0     --- End of inner exception stack trace ---    at NI.LV.FPGA.CompileWorkerUI.SimpleUowStep.Run (NI.LV.FPGA.CompileWorkerUI.UowState uowState, IDictionary`2 globalParameterList, IUowStepExecutor executor) [0x00000] in <filename unknown>:0     at NI.LV.FPGA.CompileWorkerUI.SimpleUowStep.Run (NI.LV.FPGA.CompileWorkerUI.UowState state, IDictionary`2 globalParameterList, IUowStepExecutor executor, System.Collections.Generic.SortedDictionary`2 AllSteps, System.Func`1 shouldAbort) [0x00000] in <filename unknown>:0     at NI.LV.FPGA.CompileWorkerUI.UnitOfWork.Run (IFpgaFarmCapability capabilityObject) [0x00000] in <filename unknown>:0
2019-09-30 11:16:43Z|WARN|SessionId=zglGY13|WorkerId=sMw82a8|JobId=CAl43E9|TotalBytesAttemptedToStream=26225
2019-09-30 11:16:43Z|WARN|SessionId=zglGY13|WorkerId=sMw82a8|JobId=CAl43E9|TotalBytesStreamed=26225
2019-09-30 11:16:43Z|INFO|SessionId=zglGY13|WorkerId=sMw82a8|JobId=CAl43E9|About to upload file
2019-09-30 11:16:44Z|INFO|SessionId=zglGY13|WorkerId=sMw82a8|JobId=CAl43E9|File successfully uploaded.
2019-09-30 11:16:44Z|INFO|SessionId=zglGY13|WorkerId=sMw82a8|JobId=CAl43E9|Job finished successfully.
2019-09-30 11:16:44Z|INFO|SessionId=zglGY13|WorkerId=sMw82a8|JobId=CAl43E9|Finished thread.
2019-09-30 11:16:46Z|INFO|SessionId=zglGY13|WorkerId=|JobId=|Setting info that should end up in the UI: Registered Capabilities: ( 'Xilinx 14.7'  'Xilinx 14.7 (64-bit)'  'Vivado 2017.2 (64-bit)' )
2019-09-30 11:16:46Z|INFO|SessionId=zglGY13|WorkerId=|JobId=|UI info changed: Registered Capabilities: ( 'Xilinx 14.7'  'Xilinx 14.7 (64-bit)'  'Vivado 2017.2 (64-bit)' )

 

 

 

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