I'm currently using a PXIe-8133 in a 1062 to read from a PXI-7842 RIO card. I currently have a large FIFO set up with the 'FPGA-to-Host DMA' configuration. When I add this into my core loop on my RT system, I notice it increases the average execution time of the loop by around 8uS. I'm curious now, if I want to read only 6 digital inputs from the FPGA into this data aquisition loop, what's the quickest way to do it? Am I better off using the digital inputs of say a PXIe-6363?
Are you reading digital waveforms? Or are you just trying to get the fastest update rate? How fast do you need to update the digital values?
I need to get the fastest update rate. I'm just trying to read digital inputs and/or integer values out of the FPGA without adding more than 2-3uS of execution time on the RT box.
Are you worried about missing data points? Or are you just interested in the most recent value? If you are only interested in the most recent value, you could try putting your acquisition in a parallel loop so that it doesn't slow the rest of your code down. If you are worried about missing data points, you should add a buffer to your acquisition.
I think FIFO's are a good way for you to go, and I don't think switching to the PXIe-6363 will help. Why do you need updates this fast? Perhaps there is another way we could work around this problem?
I need the current value at the time of the read. My loop rate on the RT system is my effective sample rate. My only concern is the execution time of the call to read from the FPGA. I'm trying to get my loop rate to around 100kHz, and at that level every micro-second counts.
Could you tell me a little more about your application? Why do you need this fast of a loop rate on the RT side? Could you try moving some of your code down to the FPGA? Also, how did you benchmark the digital read?
I have one or more models running on the RT side that I don't want to convert to fixed point math at this time. Plus there are other items parallel to the FPGA that need to stay in sync with it, all done via the RT loop. I'm not looking for a solution here that involves moving complexity into the FPGA; I'd simply like to optimize the FPGA digital I/O as much as possible to minimize their execution time as much as possible.
I'm benchmarking my digital reads by taking timestamps before and after the operation and comparing them after execution has completed.
I'm sorry, but I don't think there is anything we can do here to speed up digital I/O read. You can of course achieve much higher read rates if you use hardware timed acquisition, but that doesn't sound like it would work with your application.
Good luck on your project!
I'm using hardware timed acquisition with my other DAQ cards. Is it possible to do so with the FPGA card as well?
You can, but it is a little different. You have to program the buffer yourself on the FPGA using a buffered FIFO. You then read chunks of data at a time on the RT side. This will allow you to collect more data than you could if you were just reading a single point at a time in the RT program.
Best of luck on your project,