CPU-load 100% when reading a FIFO (FPGA target to RT host) cRIO NI-9073

[Martin_T]

Hi everyone,

I am (again) trying to make an application that reads a specific number of pressure samples at a fixed sample rate to a variable that my real-time application can access when needed.

My CompactRIO is a NI-9073, and I need to read at least 8 channels from a NI-9208 Analog Input module.  I want 512 samples per channel at a sampling rate of somewhere between 500-1000 Hz.

This should be a walk in the park, but the transfer of data between the target and the host is still a complete mystery to me, so I am taking this really slowly.  I am developing a small demo programme to learn, but despite of this I have ran into problems I do not understand.  I was hoping someone with the right skills could help me along…

As it is important that the data are in one continuous order, I decided only to write the samples to the FIFO when it is empty.  The logic I tried to implement is the following:

On the FPGA Target:

- When "Request to Read" is True AND FIFO is empty: Read n samples to the FIFO.

On the RT Host:

- At a given time interval (and the number of elements in the FIFO is zero) send a request to the FPGA to put the samples in the FIFO, then read the n samples into a variable, replacing the existing data in the variable.

As far as I can tell, my programmes seem to be working somehow, but there are two major problems:

1. The load of the CPU displayed in the Distributed System Manager is always bordering on 100% when the VI on the RT-Host is running. Why? This should not be a CPU-demanding application at all (especially not at the rates my demo-programme is running).

2. Some times the variable contains the data and sometimes it is empty.  I do not understand why, as I expected that the data would be replaced by the new data only.

Any thoughts on my mistakes are greatly appreciated!

Best regards,

Martin

[BuddyHaun · Accepted solution]

The following link explains the CPU usage behavior. Basically the timeouts for DMA transfers work a little differently than expected. Always create the block diagram constant of zero as shown in the example or the code will use 100% of the CPU.  Your system will poll the FIFO as fast as possible until the number of elements is reached. http://digital.ni.com/public.nsf/allkb/583DDFF1829F51C1862575AA007AC792

[Martin_T]

Excellent!  That solved my problems.  Thanks a lot!

I improved the VIs based on the ideas I got from the article you linked to, and now my application works like a charm.  I have included pictures of the modified VIs as well as a screenshot of the CPU-usage on the Real-Time Host.

Further suggestions of improvements are of course always welcome!

Best regards,
Martin