09-14-2020 04:51 AM
Hi,
I have a problem with FIFO buffer on RT target. When program is running usually everything is fine, I am reading values with requested speed. But from time to time I can notice that inside buffer stays more and more values like program can't read fast enough, buffer reaches its maximum depth and resets after a short while and then program continues running properly.
FPGA code:
RT data aquisition code:
I am using Target to Host DMA FIFO settings.
Device: cRIO-9049
Labview 2019
I am new with Labview and I would be grateful for any tips and ideas what can creates this kind of delays in code. And sorry for my language mistakes.
Solved! Go to Solution.
09-14-2020 03:49 PM
Your screenshots don't really show much of the important stuff (sample rates, buffer sizes). Also, I expect some of the people on here are far more experienced with DMA FIFO than I am and will have specific points.
I can just give you some general things to consider:
One of the problems we had was that the FIFO DMA buffer length on FPGA was too small.
For troubleshooting - it might be useful to feed an artificially created sine wave or sawtooth created on the FPGA side and see what you get out on the RT side - as that can allow you see if you are getting occassional blocks of missing data, if consistent, if applies to all signals through the buffer or all buffers.
Hope this helps,