Accessing EtherCAT data on cRIO Master's FPGA

[MarkCG]

Assuming someone had a sytem where many EtherCAT slaves where connected to the master, and you wanted to be able to access that data on the FPGA of the master to do things with it, how would you do it? From what I understand the Eth1 port on cRIOs is not connected to the FPGA fabric in any way. So would you have to push the data from the real-time side with something like a DMA FIFO , fpga front panel controls or UDVs so that the FPGA could work with it? 

[algarcia · Accepted solution]

Hi MarkCG,

As you mentioned, the way to approach this would be to get the data from a DMA FIFO:

Transferring Data between Devices or Structures Using FIFOs (FPGA Module)

http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgaconcepts/fpga_transfer_data/