9205 in cRIO-9074 : resources conflict between digital and analog inputs

[SamiBenF]

Hello all,

I am developping an application based on a cRIO 9074 with 4 9205 modules.

SW configuration is the following :

LV / RT / FPGA 8.5.1

NI RIO 2.4.0

The goal is to do analog acquisitions with pre and post trigger samples.

The trigger can be internal (analog or sw) or external. For this last case, a digital input is used on one of the modules.

By reading 2 channels on a single module, I should be able to acquire at sample rates close to 125kHz (if time between conversaions is set to 4µs of course).

Actually, I am not able to acquire faster than 1/56µs = 17.xx kHz !

After some investigations I discovered that the reading of one module's digital input was slowing down the analog inputs reading !

I attached a simple project which enables to acquire from a single module :

1. Set the requested loop rate to 30µs for instance
2. When "Read DI" button is set to Off, the actual loop rate should be 30µs as well
3. When setting "Read DI" to on, the actual loop rate should be 56. This will be the minimum possible period when the digital input is used. You should also notice that the "AI Node" indicator has a very high value, very close to the actual loop rate. This clearly shows that reading the DI has an influence on the AI reading rate.

If one has any idea about some workaround, please let me know.

At the moment, the only one I think about is to use the trigger SMB connector on the cRIO. A set of Vis is available on the NI website for that use, but the link is not valid !!

Thanks,

Sami

[ElRambo]

Hello,

What version of DAQmx are you running ?

Regards,

[SamiBenF]

MAX mentions NI-DAQmx 8.7.1f2 on my host PC. However I am wondering what would be the link between DAQmx and my cRIO problem ?

Thanks,

Sami.

[ElRambo]

Hello,

We have some known issues with DAQmx 8.7.1f2, but I doubt this is your case. However I advise you to get the latest version of it here :  NI-DAQmx 8.7.1f3 .

Moreover, could you update your version of NI-RIO to the latest one here : NI-RIO 2.4.1 .

After all these installations, could you tell me if you still encounter the same problems ?

Regards,

[Bassett_Hound]

Sami,

I don't think upgrading to NI-RIO 2.4.1 will help you in this particular case so I would hold off on trying that troubleshooting step for now.  Your correct that if your reading 9205 AI channels with 4 usec convert rates you should be able to get an aggregate rate of 250k, which for two channels would be 125k per channel.  If you add a third channel it should be 250/3 per channel, which from my understanding should include reading the DI channel.

Is it possible you could post some test code to help us all better understand how your using the IO nodes?

Basset Hound

[SamiBenF]

Thank you Hound Basset for your reply. I agree in the fact that NI RIO 2.4.1 which just add support for a FPGA board won't help.
I think you will find the test code you asked me for in my very first message.
Please let me know if you need more informations.

Sami.

[Bassett_Hound]

Sami,

I know you mentioned you were using 4 usec convert rates but the project attached has them set for 8 usec and I couldn't find anyplace where they were being set programatically.  Can you try the attached project with your module and let me know how many ticks it takes to perform the AI/DI reads?

Thanks,

Basset Hound

[SamiBenF]

Basset Hound,

You are right : the test project I posted sets the 9205 interchannel delay to 8µs (default value) instead of 4µs as I set it in my real project.

However, you can reproduce the problem even with the 8µs setting. If you want to test it with 4µs, you can just change the static setting in the project (I did it that way, not programmatically).

Thanks again,

Sami.