Hello Everyone,
for two weeks, I am trying to generate TWO CWS on Two 5644R. I got an example which is posted here, example is coded using instrument design libraries. I want to genrate triggers also, and implement it on FPGA. I need help if anyone of you can help in this application.I am currenlty trying to study VSA/VSG sample project 5644R but its FPGA programming is much diffecult. I want help in this application. I want to add a control which can control delay between two CWS.