From Saturday, Nov 23rd 7:00 PM CST - Sunday, Nov 24th 7:45 AM CST, ni.com will undergo system upgrades that may result in temporary service interruption.
We appreciate your patience as we improve our online experience.
From Saturday, Nov 23rd 7:00 PM CST - Sunday, Nov 24th 7:45 AM CST, ni.com will undergo system upgrades that may result in temporary service interruption.
We appreciate your patience as we improve our online experience.
11-08-2018 10:20 PM
Need to use 5645R PFI0 as a trigger. It needs to be used as a digital level trigger that takes an external signal as a switch. A high signal should start generation, and a low signal should stop it. Any help in this regard much appreciated.
11-12-2018 05:48 PM
You might be able to do this through script triggers. Have you tried something like this?
You might also be able to do this through the FPGA, but it would not be simple. The PFI0 is connected to the FPGA, so you might be able to use LabVIEW FPGA to customize your application. However, this would not be trivial.
11-16-2018 01:20 AM - edited 11-16-2018 01:22 AM
I implemented this using script triggers. It sort of works. I used the repeat until command and wait until commands in lieu of the unsupported if statement. However, there are strange latencies involved. When the trigger for generation comes, it has a 1.6 microsecond delay, and when the trigger for stopping generation comes, it has a 3.2 microsecond delay (including the starting delay). I cannot understand the reason of the delay. The switching needs to be on the order of 10 nanoseconds and this delay causes the minimum RF waveform generated to be >3.2 microseconds. any ideas?
Another thing to note would be the fact that i have extensively tested the trigger parameters. I varied the Duty Cycle, the trigger frequency and the generated waveform size and frequency. Nothing helped.
Any guidance would be much appreciated.
Edit: any information regarding the internal connections between the PFI0 port and the FPGA would also help, along with info as to whether the FPGA can be programmed directly using FPGA module and if it will solve my dilemma.
12-03-2018 03:34 PM
What is the duration of the signal written to RFSG?
12-03-2018 11:16 PM
we have tried many settings. currently, the signal length is 100 ns
12-04-2018 10:37 AM
Can you attach the script you are using?
03-04-2019 06:29 AM
So I have returned to said scenario. This is the script i am currently using.
script TrigTest
repeat forever
repeat until scripttrigger0
generate carrier
end repeat
wait until scripttrigger1
end repeat
end script
Previously, using a waveform length of 100 ns, the Initial delay was 1.5us and the ending delay(including the initial delay) was 3.2us.
Now, with a waveform length of 1ps. the initial waveform delay is 1.48us and the ending waveform delay is 1.649us. An interesting thing to note would be the fact that in both case above, after the falling edge, the waveform repeats for a total of 7 times.
03-04-2019 06:31 AM
A solution that reduces my initial delay and also, removes the extra delay at the end of the trigger would be ideal but i would settle for only getting the ending delay removed.
03-05-2019 05:05 PM
HanzalaS,
Would you be able to post a snippet of your code so that we can see how you are implementing the script trigger?
03-06-2019 06:09 AM
Uploading the code as requested.
The start trigger as stated before, has a delay of 1.48uS and at the end, we have a delay of 170ns (Variable. 170ns for a waveform size of 1.1ps). This ending delay needs to be finished. During experimentation, it was found that the after the the trigger is turned off, there is a repetition of 7 waveform iterations. it is always included, no matter the waveform length.